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1 contents ? chapter ? 1 de2 \ 115 ? package ............................................................................... 4 1.1 package contents ........................................................................................................... ............................ 4 1.2 the de2-115 board assembly ................................................................................................. .................. 5 1.3 getting help ............................................................................................................................................... 6 chapter ? 2 introduction ? of ? the ? altera ? de2 \ 115 ? board .......................................... 7 2.1 layout and components............................................................................................................................. 7 2.2 block diagram of the de2-115 board ......................................................................................... .............. 9 2.3 power-up the de2-115 board ................................................................................................. ................. 12 chapter ? 3 de2 \ 115 ? control ? panel ..................................................................... 14 3.1 control panel setup.................................................................................................................................. 14 3.2 controlling the leds, 7-segment displays and lcd display .............................................................. 16 3.3 switches and push-buttons .................................................................................................. ..................... 18 3.4 sdram/sram/eeprom/flash controller and program-mer .............................................................. 19 3.5 usb monitoring ....................................................................................................................................... 21 3.6 ps/2 device ................................................................................................................ .............................. 22 3.7 sd card .................................................................................................................................................... 23 3.8 rs-232 communication ....................................................................................................... .................... 23 3.9 vga ........................................................................................................................ ................................. 24 3.10 hsmc..................................................................................................................................................... 25 3.11 ir receiver ............................................................................................................... .............................. 26 3.12 overall structure of the de2-115 control panel............................................................................ ........ 27 chapter ? 4 using ? the ? de2 \ 115 ? board ................................................................. 29 4.1 configuring the cyclone iv e fpga.......................................................................................... ............. 29 4.2 using push-buttons and switches ............................................................................................ ................ 32 2 4.3 using leds .............................................................................................................................................. 34 4.4 using the 7-segment displays ............................................................................................... ................... 36 4.5 clock circuitry ......................................................................................................................................... 38 4.6 using the lcd module ............................................................................................................................ 39 4.7 high speed mezzanine card .................................................................................................. .................. 40 4.8 using the expansion header ................................................................................................. ................... 45 4.9 using 14-pin general purpose i/o connector................................................................................. ......... 50 4.10 using vga................................................................................................................. ............................ 51 4.11 using the 24-bit audio codec .............................................................................................. ............... 53 4.12 rs-232 serial port........................................................................................................ .......................... 54 4.13 ps/2 serial port ...................................................................................................................................... 55 4.14 gigabit ethern et transceiver .............................................................................................. .................... 56 4.15 tv decoder ................................................................................................................ ............................ 59 4.16 implementing a tv encoder ................................................................................................. ................. 60 4.17 using the usb interface................................................................................................... ...................... 61 4.18 using ir .................................................................................................................. ............................... 62 4.19 using sram/sdram/flash/eeprom/sd card ............................................................................. 63 chapter ? 5 de2 \ 115 ? system ? builder................................................................... 70 5.1 introduction .............................................................................................................................................. 70 5.2 general design flow........................................................................................................ ........................ 70 5.3 using de2-115 system builder ............................................................................................... ................ 71 chapter ? 6 examples ? of ? advanced ? demonstrations ........................................... 77 6.1 de2-115 factory configuration .............................................................................................. ................. 77 6.2 tv box demonstration ....................................................................................................... ..................... 78 6.3 usb paintbrush ............................................................................................................. ........................... 80 6.4 usb device ................................................................................................................. ............................. 82 6.5 a karaoke machine .......................................................................................................... ........................ 84 6.6 sd card demonstration ...................................................................................................... ..................... 86 6.7 sd card music pl ayer .............................................................................................................................. 89 6.8 ps/2 mouse demonstration................................................................................................... ................... 93 3 6.9 ir receiver demonstration .................................................................................................. .................... 96 6.10 music synthesizer demonstration........................................................................................... ............. 100 6.11 audio recording and playing............................................................................................... ................ 103 6.12 web server demonstration................................................................................................................... 106 chapter ? 7 appendix ....................................................................................... 115 7.1 revision history..................................................................................................................................... 115 7.2 copyright statement ............................................................................................................................... 115 ? 4 ? chapter 1 de2-115 package the de2-115 package contains all components needed to use the de2-115 board in conjunction with a computer that runs the microsoft windows os. 1 1 . . 1 1 p p a a c c k k a a g g e e c c o o n n t t e e n n t t s s figure 1-1 shows a photograph of the de2-115 package. figure 1-1 the de2-115 package contents the de2-115 package includes: ? the de2-115 board. ? usb cable for fpga programming and control. ? de2-115 system cd containing the de2-115 documentation and supporting materials, including the user manual, the control panel, system builder and altera monitor program utility, reference designs and dem onstrations, device datasheets, tuto rials, and a set of laboratory exercises. ? cd-roms containing altera?s quartus? ii web edition and the nios? ii embedded design suit evaluation edition software. 5 ? bag of six rubber (silicon) covers for the de2- 115 board stands. the bag also contains some extender pins, which can be used to facilitate easier probing with testing equipment of the board?s i/o expansion headers. ? clear plastic cover for the board. ? 12v dc desktop power supply. ? remote controller 1 1 . . 2 2 t t h h e e d d e e 2 2 - - 1 1 1 1 5 5 b b o o a a r r d d a a s s s s e e m m b b l l y y to assemble the included stands for the de2-115 board: ? assemble a rubber (silicon) cover, as shown in figure 1-2 , for each of the six copper stands on the de2-115 board ? the clear plastic cover provides extra protection, and is m ounted over the top of the board by using additional stands and screws figure 1-2 the feet for the de2-115 board 6 1 1 . . 3 3 g g e e t t t t i i n n g g h h e e l l p p here are the addresses where you can ge t help if you encounter any problem: ? altera corporation 101 innovation drive san jose, california, 95134 usa email: university@altera.com ? terasic technologies no. 356, sec. 1, fusing e. rd. jhubei city, hsinchu county, taiwan, 302 email: support@terasic.com tel.: +886-3-550-8800 web: de2-115.terasic.com 7 chapter 2 introduction of the altera de2-115 board this chapter presents the features and design characteristics of the de2-115 board. 2 2 . . 1 1 l l a a y y o o u u t t a a n n d d c c o o m m p p o o n n e e n n t t s s a photograph of the de2-1 15 board is shown in figure 2-1 and figure 2-2 . it depicts the layout of the board and indicates th e location of the connect ors and key com ponents. figure 2-1 the de2-115 board (top view) 8 figure 2-2 the de2-115 board (bottom view) the de2-115 board has many features that allow users to implement a wide range of designed circuits, from simple circuits to various multimedia projects. the following hardware is provided on the de2-115 board: ? altera cyclone? iv 4ce115 fpga device ? altera serial configur ation device ? epcs64 ? usb blaster (on board) for programming; bot h jtag and active serial (as) programming modes are supported ? 2mb sram ? two 64mb sdram ? 8mb flash memory ? sd card socket ? 4 push-buttons ? 18 slide switches ? 18 red user leds ? 9 green user leds ? 50mhz oscillator for clock sources ? 24-bit cd-quality audio c odec with line-in, line- out, and microphone-in jacks ? vga dac (8-bit high-speed triple dacs) with vga-out connector ? tv decoder (ntsc/pal/secam) and tv-in connector ? 2 gigabit ethernet phy with rj45 connectors ? usb host/slave controller with usb type a and type b connectors ? rs-232 transceiver and 9-pin connector ? ps/2 mouse/keyboard connector ? ir receiver ? 2 sma connectors for external clock input/output 9 ? one 40-pin expansion header with diode protection ? one high speed mezzanine card (hsmc) connector ? 16x2 lcd module in addition to these hardware features, the de2- 115 board has software support for standard i/o interfaces and a control panel f acility for accessing various components. also, the software is provided for supporting a number of demonstrations that illustrate the advanced capabilities of the de2-115 board. in order to use the de2-115 board, the user has to be familiar with the quartus ii software. the necessary knowledge can be acqui red by reading the tutorials ? getting started with altera?s de2-115 board ? (tut_initialde2-115.pdf) and ? quartus ii introduction (which exists in three versions based on the design entry method used, namely verilog, vhdl or schematic entry). these tutorials are provided in the directory de2_115_tutorials on the de2-115 system cd that accompanies the de2-115 kit and can also be found on terasic?s de2-115 web pages . 2 2 . . 2 2 b b l l o o c c k k d d i i a a g g r r a a m m o o f f t t h h e e d d e e 2 2 - - 1 1 1 1 5 5 b b o o a a r r d d figure 2-3 gives the block diagram of the de2-115 boa rd. to provide maximum flexibility for the user, all connections are made through the cyclone iv e fpga device. thus, the user can configure the fpga to implement any system design. figure 2-3 block diagram of de2-115 10 following is more detailed information about the blocks in figure 2-3 : f f p p g g a a d d e e v v i i c c e e ? cyclone iv ep4ce115f29 device ? 114,480 les ? 432 m9k memory blocks ? 3,888 kbits embedded memory ? 4 plls f f p p g g a a c c o o n n f f i i g g u u r r a a t t i i o o n n ? jtag and as mode configuration ? epcs64 serial configuration device ? on-board usb blaster circuitry m m e e m m o o r r y y d d e e v v i i c c e e s s ? 128mb (32mx32bit) sdram ? 2mb (1mx16) sram ? 8mb (4mx16) flash with 8-bit mode ? 32kb eeprom s s d d c c a a r r d d s s o o c c k k e e t t ? provides spi and 4-bit sd mode for sd card access c c o o n n n n e e c c t t o o r r s s ? two ethernet 10/100/1000 mbps ports ? high speed mezzanine card (hsmc) ? configurable i/o standards (voltage levels:3.3/2.5/1.8/1.5v) ? usb type a and b o provide host and device contro llers compliant with usb 2.0 o support data transfer at full-speed and low-speed o pc driver available 11 ? 40-pin expansion port o configurable i/o standards (voltage levels:3.3/2.5/1.8/1.5v) ? vga-out connector o vga dac (high speed triple dacs) ? db9 serial connector for rs-232 port with flow control ? ps/2 mouse/keyboard c c l l o o c c k k ? three 50mhz oscillator clock inputs ? sma connectors (externa l clock input/output) a a u u d d i i o o ? 24-bit encoder/decoder (codec) ? line-in, line-out, and microphone-in jacks d d i i s s p p l l a a y y ? 16x2 lcd module s s w w i i t t c c h h e e s s a a n n d d i i n n d d i i c c a a t t o o r r s s ? 18 slide switches and 4 push-buttons switches ? 18 red and 9 green leds ? eight 7-segment displays o o t t h h e e r r f f e e a a t t u u r r e e s s ? infrared remote-control receiver module ? tv decoder (ntsc/pal/secam) and tv-in connector 12 p p o o w w e e r r ? desktop dc input ? switching and step-down regulators lm3150mh 2 2 . . 3 3 p p o o w w e e r r - - u u p p t t h h e e d d e e 2 2 - - 1 1 1 1 5 5 b b o o a a r r d d the de2-115 board comes with a preloaded configur ation bit stream to dem onstrate some features of the board. this bit stream also allows users to see quickly if the board is working properly. to power-up the board perform the following steps: 1. connect the provided usb cable from the host computer to the usb blaster connector on the de2-115 board. for communication between the host and the de2-115 board, it is necessary to install the altera usb blaster driver software . if this driver is not already installed on the host computer, it can be installed as explained in the tutorial ? getting started with altera's de2-115 board ? (tut_initialde2-115.pdf). this tutorial is available in the directory de2_115_tutorials on the de2-115 system cd. 2. turn off the power by pressing the red on/off switch before connectin g the 12v adapter to the de2-115 board. 3. connect a vga monitor to the vga port on the de2-115 board. 4. connect your headset to the line-o ut audio port on the de2-115 board. 5. turn the run/prog switch (sw19) on the left edge of the de2-115 board to run position; the prog position is used only for the as mode programming. 6. recycle the power by turning the red power switch on the de2- 115 board off and on again . at this point you should observe the following: ? all user leds are flashing ? all 7-segment displays are cycling through the numbers 0 to f ? the lcd display shows ?welcome to the altera de2-115? ? the vga monitor displays the image shown in figure 2-4 ? set the slide switch sw 17 to the down position; you should hear a 1-khz sound. be careful of the very loud volume for avoiding any discomfort ? set the slide switch sw17 to the up position and connect the output of an audio player to the line-in connector on the de2-115 board; on your sp eaker or headset you should hear the music played from the audio player (mp3, pc, ipod, or the like) 13 ? you can also connect a microphone to the mi crophone-in connector on the de2-115 board; your voice will be mixed with the mu sic playing on the audio player figure 2-4 the default vga output pattern 14 chapter 3 de2-115 control panel the de2-115 board comes with a control panel facility that allows us ers to access various components on the board from a host computer. th e host computer communi cates with the board through a usb connection. the facility can be used to verify the functionality of components on the board or be used as a debug t ool while developing rtl code. this chapter first presents some basic functions of the control panel, then describes its structure in block diagram form, and finally describes its capabilities. 3 3 . . 1 1 c c o o n n t t r r o o l l p p a a n n e e l l s s e e t t u u p p the control panel software utilit y is located in the directory ?de2_115_tools/de2_115_control_panel ? in the de2-115 system cd . it's free of installation, just copy the whole folder to your host computer and launch the control panel by executing the ?de2_115_controlpanel.exe?. (windows 7 64-bit users: if an error message that shows a missing jtag_client.dll file (cannot find jtag_client.dll) while the control panel is commencing, users should re-launch the de4_controlpanel.exe from the following directory (/de2_115_tools/de2_115_contro l_panel/win7_64bits)) specific control circuit should be downloaded to your fpga board before the control panel can request it to perform required tasks. the program will call quartus ii tools to download the control circuit to the fpga board through usb-blaster[usb-0] connection. to activate the control panel, perform the following steps: 1. make sure quartus ii 10.0 or later ve rsion is installed su ccessfully on your pc. 2. set the run/prog switch to the run position. 3. connect the supplied usb cable to the usb bl aster port, connect the 12v power supply, and turn the power switch on. 4. start the executable de2_115_controlpanel.exe on the host computer. th e control panel user interface shown in figure 3-1 will a ppear. 15 5. the de2_115_controlpanel.sof bit stream is load ed automatically as soon as the de2_115_control_panel.exe is launched. 6. in case the connection is disc onnected, click on connect wher e the .sof will be re-loaded onto the board. 7. note, the control panel will occupy the usb port until you close that port; you cannot use quartus ii to download a configuration file into the fpga until the usb port is closed. 8. the control panel is now ready for use; expe rience it by setting the on/off status for some leds and observing the result on the de2-115 board. figure 3-1 the de2-115 control panel the concept of the de2-115 c ontrol panel is illustrated in figure 3-2 . the ?control circuit? that perform s the control functions is implemented in the fpga board. it communicates with the control panel window, which is active on the host computer, via the usb blaster link. the graphical interface is used to issue commands to the control circuit. it handles all requests and performs data transfers between th e computer and the de2-115 board. 16 figure 3-2 the de2-115 control panel concept the de2-115 control panel can be used to li ght up leds, change the values displayed on 7-segment and lcd displays, monitor buttons/sw itches status, read/write the sdram, sram, eeprom and flash memory, monitor the status of an usb device, communicate with the ps/2 mouse, output vga color pattern to vga monitor, verify functiona lity of hsmc connector i/os, communicate with pc via rs-232 interface and read sd card specification information. the feature of reading/writing a word or an entire file from/to the flash memory allows the user to develop multimedia applications (f lash audio player, flash pictur e viewer) without worrying about how to build a memory programmer. 3 3 . . 2 2 c c o o n n t t r r o o l l l l i i n n g g t t h h e e l l e e d d s s , , 7 7 - - s s e e g g m m e e n n t t d d i i s s p p l l a a y y s s a a n n d d l l c c d d d d i i s s p p l l a a y y a simple function of the control panel is to allow setting the values displayed on leds, 7-segment displays, and the lcd character display. choosing the led tab leads to the window in figure 3-3 . here, you can directly turn the leds on or of f individually or by clicking ?light all? or ?unlight all?. 17 figure 3-3 controlling leds choosing the 7-seg tab leads to the window shown in figure 3-4 . from the window , directly use the left-right arrows to control the 7-seg pa tterns on the de2-115 board which are updated immediately. note that the dots of the 7-segs are not enabled on de2-115 board. figure 3-4 controlling 7-seg display 18 choosing the lcd tab leads to the window in figure 3-5 . t ext can be written to the lcd display by typing it in the lcd box then pressing the set button. figure 3-5 controlling the lcd display the ability to set arbitrary values into simple display devices is not n eeded in typical design activities. however, it gives the user a simple mechanism for verifying that these devices are functioning correctly in case a malfunction is su spected. thus, it can be used for troubleshooting purposes. 3 3 . . 3 3 s s w w i i t t c c h h e e s s a a n n d d p p u u s s h h - - b b u u t t t t o o n n s s choosing the switches tab leads to the window in figure 3-6 . the function is designed to m onitor the status of slide switches and push-buttons in re al time and show the stat us in a graphical user interface. it can be used to verify the func tionality of the slide switches and push-buttons. 19 figure 3-6 monitoring switches and buttons the ability to check the status of push-button a nd slide switch is not needed in typical design activities. however, it provides users a simple mech anism for verifying if th e buttons and switches are functioning correctly. thus, it can be used for troubleshooting purposes. 3 3 . . 4 4 s s d d r r a a m m / / s s r r a a m m / / e e e e p p r r o o m m / / f f l l a a s s h h c c o o n n t t r r o o l l l l e e r r a a n n d d p p r r o o g g r r a a m m - - m m e e r r the control panel can be used to write/read data to/from the sdram, sram, eeprom, and flash chips on the de2-115 board. as an exampl e, we will describe how the sdram may be accessed; the same approach is used to access the sram, eeprom, and flash. click on the memory tab and select ?sdram? to reach the window in figure 3-7 . 20 figure 3-7 accessing the sdram a 16-bit word can be written in to the sdram by entering the a ddress of the desired location, specifying the data to be written, and pressing the wr ite button. contents of the location can be read by pressing the read button. figure 3-7 depicts the result of writing the hexadecim al value 06ca into offset address 200, followed by reading the same location. the sequential write function of the control panel is used to write the contents of a file into the sdram as follows: 1. specify the starting addr ess in the address box. 2. specify the number of bytes to be written in the lengt h box. if the entire file is to be loaded, then a checkmark may be placed in the file le ngth box instead of giving the number of bytes. 3. to initiate the writing process, clic k on the write a file to memory button. 4. when the control panel responds with the st andard windows dialog box asking for the source file, specify the desired f ile in the usual manner. the control panel also supports lo ading files with a .hex extension. files with a .hex extension are ascii text files that specify memory values us ing ascii characters to represent hexadecimal values. for example, a file containing the line 0123456789abcdef defines eight 8-bit values: 01, 23, 45, 67, 89, ab, cd, ef. these values will be loaded consecutively into the memory. 21 the sequential read function is used to read the c ontents of the sdram and fill them into a file as follows: 1. specify the starting addr ess in the address box. 2. specify the number of bytes to be copied into the file in the length bo x. if the entire contents of the sdram are to be copied (which involv es all 128 mbytes), then place a checkmark in the entire memory box. 3. press load memory co ntent to a file button. 4. when the control panel responds with the standard windows dialog box asking for the destination file, specify the desired file in the usual manner. users can use the similar way to access the sram, eeprom and flash. please note that users need to erase the flash before writing data to it. 3 3 . . 5 5 u u s s b b m m o o n n i i t t o o r r i i n n g g the control panel provides users a usb monitori ng tool which monitors the status of the usb devices connected to the usb por t on the de2-115 board. by plugging in a usb device to the usb host port of the board, the device type is displayed on the control window. figure 3-8 shows a usb mouse plugged into the host usb port. figure 3-8 usb mouse monitoring tool 22 3 3 . . 6 6 p p s s / / 2 2 d d e e v v i i c c e e the control panel provides users a ps/2 monitoring to ol which monitors the real-time status of a ps/2 mouse connected to the de2-115 board. the m ovement of the mouse and the status of the three buttons will be shown in the graphical and te xt interface. the mouse movement is translated as a position (x,y) with range from (0,0)~(1023,767) . this function can be used to verify the functionality of th e ps/2 connection. follow the steps below to exercise the ps/2 mouse monitoring tool: 1. choosing the ps/2 tab le ads to the window in figure 3-9 . 2. plug a ps/2 mouse to the ps/2 port on the de2-115 board. 3. press the start button to start the ps/2 mouse monitoring process, and the button caption is changed from start to stop. in the monitoring pro cess, the status of the ps/2 mouse is updated and shown in the control panel?s gui window in real-time. press stop to terminate the monitoring process. figure 3-9 ps/2 mouse monitoring tool 23 3 3 . . 7 7 s s d d c c a a r r d d the function is designed to read the identificati on and specification inform ation of the sd card. the 4-bit sd mode is used to access the sd ca rd. this function can be used to verify the functionality of the sd card interface. follow the steps belo w to exercise the sd card: 1. choosing the sd card tab leads to the window in figure 3-10. 2. insert an sd card to the de2-115 board, and th en press the read button to read the sd card. the sd card?s identification, specification, and f ile format information will be displayed in the control window. figure 3-10 reading the sd card identification and specification 3 3 . . 8 8 r r s s - - 2 2 3 3 2 2 c c o o m m m m u u n n i i c c a a t t i i o o n n the control panel allows users to verify the ope ration of the rs-232 serial communication interface on the de2-115. the setup is established by connec ting a rs-232 9-pin male to female cable from the pc to the rs-232 port where the control panel communicates to the terminal emulator software on the pc, or vice versa. alterna tively, a rs-232 loopback cable can also be us ed if you do not wish to use the pc to verify the test. the receive te rminal window on the control panel monitors the serial communication status. follow the steps be low to initiate the rs-232 communication: 24 1. choosing the rs-232 tab leads to the window in figure 3-11. 2. plug in a rs-232 9-pin male to female cable from pc to rs-232 port or a rs-232 loopback cable directly to rs-232 port. 3. the rs-232 settings are provided below in case a connection from the pc is used: ? baud rate: 115200 ? parity check bit: none ? data bits: 8 ? stop bits: 1 ? flow control (cts/rts): on 4. to begin the communication, enter specific letters follo wed by clicking send. during the communication process, observe the status of the receive terminal window to verify its operation. figure 3-11 rs-232 serial communication 3 3 . . 9 9 v v g g a a de2-115 control panel provides vga pattern function that allows users to output color pattern to lcd/crt monitor using the de2-115 board. follow the steps below to generate the vga pattern function: 25 1. choosing the vga tab leads to the window in figure 3-12. 2. plug a d-sub cable to vga connector of the de2-115 board and lcd/crt monitor. 3. the lcd/crt monitor will display the same color pattern on the control panel window. 4. click the drop down menu shown in figure 3-12 where y ou can output the selected color individually. figure 3-12 controlling vga display 3 3 . . 1 1 0 0 h h s s m m c c select the hsmc tab to reach the window shown in figure 3-13 . this function is designed to verify the functionality of the signals located on th e hsmc connector . before running the hsmc loopback verification test, follow the instruction noted under the loopback installation section and click on verify. please note to turn off the de2-1 15 board before the hsmc loopback adapter is installed to prevent any damage to the board. the hsmc loopback adapter is not provided in the kit package but can be purchased through the website below: ( http://www.terasic.com.tw/cgi-bin/page/arc hive.pl? language=english&categoryno=78&no=495 ) 26 figure 3-13 hsmc loopback verification test performed under control panel 3 3 . . 1 1 1 1 i i r r r r e e c c e e i i v v e e r r from the control panel, we can test the ir re ceiver on the de2-115 by sending scan code from a remote controller. figure 3-14 depicts the ir receiver window when the ir tab is pressed. w hen the scan code is received, the information will be displayed on the ir receiver window represented in hexadecimal. also, the pressed button on the remote controller will be indicated on the graphic of remote controller on the ir receiver window. note that there exists several encoding form among different brands of remote controll ers. only the remote controller co mes with the kit is confirmed to be compatible with this software. 27 figure 3-14 testing the ir receiver using remote controller 3 3 . . 1 1 2 2 o o v v e e r r a a l l l l s s t t r r u u c c t t u u r r e e o o f f t t h h e e d d e e 2 2 - - 1 1 1 1 5 5 c c o o n n t t r r o o l l p p a a n n e e l l the de2-115 control panel is based on a nios ii so pc system instantiated in the cyclone iv e fpga with software running on the on-chip memory. the software part is implemented in c code; the hardware part is implemented in verilog hdl code with sopc builder. the source code is not available on the de2_115 system cd. to run the control panel, users should make the configuration according to section 3.1. figure 3-15 depicts the structure of the control panel. each input/output device is controlled by the nios ii processor instantiated in the fpga chip. the communication with the pc is done via the usb blaster link. the nios ii interprets the commands sent from the pc and pe rforms the corresponding actions. 28 figure 3-15 the block diagram of the de2-115 control panel 29 chapter 4 using the de2-115 board this chapter gives instructions for using the de 2-115 board and describes each of its peripherals. 4 4 . . 1 1 c c o o n n f f i i g g u u r r i i n n g g t t h h e e c c y y c c l l o o n n e e i i v v e e f f p p g g a a the procedure for downloading a circuit from a host computer to the de2-115 board is described in the tutorial quartus ii introducti on. this tutorial is found in th e de2_115_tutorials folder on the de2-115 system cd. the user is encouraged to r ead the tutorial first, and treat the information below as a short reference. the de2-115 board contains a serial configurati on device that stores configuration data for the cyclone iv e fpga. this configurat ion data is automatically loaded from the configuration device into the fpga every time while power is applied to the board. using the quartus ii software, it is possible to reconfigure the fpga at any time, and it is also possible to cha nge the non-volatile data that is stored in the serial configuration devi ce. both types of program ming methods are described below. 1. jtag programming: in this method of progr amming, named after the ieee standards joint test action group, the configuration bit stream is downloaded directly into the cyclone iv e fpga. the fpga will retain this configuration as long as power is applied to the board; the configuration information will be lost when the power is turned off. 2. as programming: in this method, called activ e serial programming, the configuration bit stream is downloaded into the altera epcs 64 serial configuratio n device. it provides non-volatile storage of the bit stream, so that th e information is retained even when the power supply to the de2-115 board is turned off. when the board?s po wer is turned on, the configuration data in the epcs64 device is auto matically loaded into the cyclone iv e fpga. ? jtag chain on de2-115 board to use jtag interface for configuring fpga de vice, the jtag chain on de2-115 must form a close loop that allows quartus ii programmer to detect fpga device. figure 4-1 illu strates the jtag chain on de2-115 board. shorting pin1 and pi n2 on jp3 can disable the jtag signals on 30 hsmc connector that will form a clos e jtag loop chain on de2-115 board (see figure 4-2 ). thus, only the on board fpga device (cyclone iv e) will be detected by quartus ii programmer. if users want to include another fpga de vice or interface containing fpg a device in the chain via hsmc connector, short pin2 and pin3 on jp3 to enable the jtag signal ports on the hsmc connector. figure 4-1 the jtag chain on de2-115 board figure 4-2 the jtag chain configuration header the sections below describe the steps used to perform both jtag and as programming. for both methods the de2-115 board is connect ed to a host computer via a us b cable. using this connection, the board will be identified by the host computer as an altera usb blaster device. the process for installing on the host computer the necessary soft ware device driver that communicates with the usb blaster is described in the tutorial ? getting started with altera?s de2-115 board? (tut_initialde2-115.pdf). this tutorial is available on the de2-115 system cd. 31 ? configuring the fpga in jtag mode figure 4-3 illustrates the jtag configuration setup. to download a configuration bit stream into the cyclone iv e fpga, perform the following steps: ? ensure that power is applied to the de2-115 board ? configure the jtag programming circuit by setti ng the run/prog slide switch (sw19) to the run position (see figure 4-4 ) ? connect the supplied us b cable to the usb blaster port on the de2-115 board (see figure 2-1 ) ? the fpga c an now be programmed by using th e quartus ii programmer to select a configuration bit stream file w ith the .sof filename extension figure 4-3 the jtag configuration scheme figure 4-4 the run/prog switch (sw19) is set in jtag mode 32 ? configuring the epcs64 in as mode figure 4-5 illustrates the as configuration setup. to download a configuration bit stream into the epcs64 serial configuration devi ce, perform the following steps: ? ensure that power is applied to the de2-115 board. ? connect the supplied usb cable to the usb blaster port on the de2-115 board (see figure 4-5 ) ? configure the jtag programm ing circuit by setti ng the run/prog slide switch (sw19) to the prog position. ? the epcs64 chip can now be programmed by us ing the quartus ii programmer to select a configuration bit stream file w ith the .pof filena me extension. ? once the programming operation is finished, set the run/prog slide switch back to the run position and then reset the board by turning the po wer switch off and back on; this action causes the new configuration data in the epcs64 de vice to be loaded into the fpga chip. figure 4-5 the as configuration scheme 4 4 . . 2 2 u u s s i i n n g g p p u u s s h h - - b b u u t t t t o o n n s s a a n n d d s s w w i i t t c c h h e e s s the de2-115 board provides four push-button switches as shown in figure 4-6 . e ach of these switches is debounced using a schmitt tr igger circuit, as indicated in figure 4-7 . the four out puts called key0, key1, key2, and key3 of the schmitt trigger devices are conne cted directly to the cyclone iv e fpga. each push-button switch provi des a high logic level when it is not pressed, and provides a low logic level when depressed. si nce the push-button switches are debounced, they are appropriate for using as cloc k or reset inputs in a circuit. 33 figure 4-6 connections between the push-button and cyclone iv e fpga pushbutton released pushbutton depressed before debouncing schmitt trigger debounced figure 4-7 switch debouncing there are also 18 slide switche s on the de2-115 board (see figure 4-8 ). these s witches are not debounced, and are assumed for use as level-sensitiv e data inputs to a circ uit. each switch is connected directly to a pin on the cyclone iv e fpga. when the switch is in the down position (closest to the edge of the board), it provides a low logic level to the fpga, and when the switch is in the up position it provides a high logic level. 34 figure 4-8 connections between the slide switches and cyclone iv e fpga 4 4 . . 3 3 u u s s i i n n g g l l e e d d s s there are 27 user-controllable leds on the de2-1 15 board. eighteen red led s are situated above the 18 slide switches, and eight green leds are found above the push-button switches (the 9th green led is in the middle of the 7-segment displays ). each led is driven directly by a pin on the cyclone iv e fpga; driving its as sociated pin to a high logic level turns the led on, and driving the pin low turns it off. figure 4-9 sh ows the connections between leds and cyclone iv e fpga. figure 4-9 connections between the leds and cyclone iv e fpga a list of the pin names on the cyclone iv e fpga th at are connected to the slide switches is given in table 4-1 . sim ilarly, the pins used to connect to the push-button switches and leds are displayed in table 4-2 and table 4-3 , respec tively. 35 table 4-1 pin assignments for slide switches signal name fpga pin no. description i/o standard sw[0] pin_ab28 slide switch[0] depending on jp7 sw[1] pin_ac28 slide switch[1] depending on jp7 sw[2] pin_ac27 slide switch[2] depending on jp7 sw[3] pin_ad27 slide switch[3] depending on jp7 sw[4] pin_ab27 slide switch[4] depending on jp7 sw[5] pin_ac26 slide switch[5] depending on jp7 sw[6] pin_ad26 slide switch[6] depending on jp7 sw[7] pin_ab26 slide switch[7] depending on jp7 sw[8] pin_ac25 slide switch[8] depending on jp7 sw[9] pin_ab25 slide switch[9] depending on jp7 sw[10] pin_ac24 slide switch[10] depending on jp7 sw[11] pin_ab24 slide switch[11] depending on jp7 sw[12] pin_ab23 slide switch[12] depending on jp7 sw[13] pin_aa24 slide switch[13] depending on jp7 sw[14] pin_aa23 slide switch[14] depending on jp7 sw[15] pin_aa22 slide switch[15] depending on jp7 sw[16] pin_y24 slide switch[16] depending on jp7 sw[17] pin_y23 slide switch[17] depending on jp7 table 4-2 pin assignments for push-buttons signal name fpga pin no. description i/o standard key[0] pin_m23 push-button[0] depending on jp7 key[1] pin_m21 push-button[1] depending on jp7 key[2] pin_n21 push-button[2] depending on jp7 key[3] pin_r24 push-button[3] depending on jp7 table 4-3 pin assignments for leds signal name fpga pin no. description i/o standard ledr[0] pin_g19 led red[0] 2.5v ledr[1] pin_f19 led red[1] 2.5v ledr[2] pin_e19 led red[2] 2.5v ledr[3] pin_f21 led red[3] 2.5v ledr[4] pin_f18 led red[4] 2.5v ledr[5] pin_e18 led red[5] 2.5v ledr[6] pin_j19 led red[6] 2.5v ledr[7] pin_h19 led red[7] 2.5v ledr[8] pin_j17 led red[8] 2.5v ledr[9] pin_g17 led red[9] 2.5v ledr[10] pin_j15 led red[10] 2.5v ledr[11] pin_h16 led red[11] 2.5v ledr[12] pin_j16 led red[12] 2.5v ledr[13] pin_h17 led red[13] 2.5v ledr[14] pin_f15 led red[14] 2.5v 36 ledr[15] pin_g15 led red[15] 2.5v ledr[16] pin_g16 led red[16] 2.5v ledr[17] pin_h15 led red[17] 2.5v ledg[0] pin_e21 led green[0] 2.5v ledg[1] pin_e22 led green[1] 2.5v ledg[2] pin_e25 led green[2] 2.5v ledg[3] pin_e24 led green[3] 2.5v ledg[4] pin_h21 led green[4] 2.5v ledg[5] pin_g20 led green[5] 2.5v ledg[6] pin_g22 led green[6] 2.5v ledg[7] pin_g21 led green[7] 2.5v ledg[8] pin_f17 led green[8] 2.5v 4 4 . . 4 4 u u s s i i n n g g t t h h e e 7 7 - - s s e e g g m m e e n n t t d d i i s s p p l l a a y y s s the de2-115 board has eight 7-segment displays. th ese displays are arranged into two pairs and a group of four, behaving the intent of displaying numbers of various sizes. as indicated in the schematic in figure 4-10 , the seven segm ents (common anode) are connected to pins on cyclone iv e fpga. applying a low logic level to a segm ent will light it up and applying a high logic level turns it off. each segment in a display is identified by an index from 0 to 6, with the positions given in figure 4-10. table 4-4 shows the assignm ents of fpga pi ns to the 7-segment displays. figure 4-10 connections between the 7-segment display hex0 and cyclone iv e fpga table 4-4 pin assignments for 7-segment displays signal name fpga pin no. description i/o standard hex0[0] pin_g18 seven se gment digit 0[0] 2.5v hex0[1] pin_f22 seven se gment digit 0[1] 2.5v hex0[2] pin_e17 seven se gment digit 0[2] 2.5v hex0[3] pin_l26 seven segment digit 0[3] depending on jp7 hex0[4] pin_l25 seven segment digit 0[4] depending on jp7 37 hex0[5] pin_j22 seven segment digit 0[5] depending on jp7 hex0[6] pin_h22 seven segment digit 0[6] depending on jp7 hex1[0] pin_m24 seven segment digit 1[0] depending on jp7 hex1[1] pin_y22 seven segment digit 1[1] depending on jp7 hex1[2] pin_w21 seven segment digit 1[2] depending on jp7 hex1[3] pin_w22 seven segment digit 1[3] depending on jp7 hex1[4] pin_w25 seven segment digit 1[4] depending on jp7 hex1[5] pin_u23 seven segment digit 1[5] depending on jp7 hex1[6] pin_u24 seven segment digit 1[6] depending on jp7 hex2[0] pin_aa25 seven segment digit 2[0] depending on jp7 hex2[1] pin_aa26 seven segment digit 2[1] depending on jp7 hex2[2] pin_y25 seven segment digit 2[2] depending on jp7 hex2[3] pin_w26 seven segment digit 2[3] depending on jp7 hex2[4] pin_y26 seven segment digit 2[4] depending on jp7 hex2[5] pin_w27 seven segment digit 2[5] depending on jp7 hex2[6] pin_w28 seven segment digit 2[6] depending on jp7 hex3[0] pin_v21 seven segment digit 3[0] depending on jp7 hex3[1] pin_u21 seven segment digit 3[1] depending on jp7 hex3[2] pin_ab20 seven segment digit 3[2] depending on jp6 hex3[3] pin_aa21 seven segment digit 3[3] depending on jp6 hex3[4] pin_ad24 seven segment digit 3[4] depending on jp6 hex3[5] pin_af23 seven segment digit 3[5] depending on jp6 hex3[6] pin_y19 seven segment digit 3[6] depending on jp6 hex4[0] pin_ab19 seven segment digit 4[0] depending on jp6 hex4[1] pin_aa19 seven segment digit 4[1] depending on jp6 hex4[2] pin_ag21 seven segment digit 4[2] depending on jp6 hex4[3] pin_ah21 seven segment digit 4[3] depending on jp6 hex4[4] pin_ae19 seven segment digit 4[4] depending on jp6 hex4[5] pin_af19 seven segment digit 4[5] depending on jp6 hex4[6] pin_ae18 seven segment digit 4[6] depending on jp6 hex5[0] pin_ad18 seven segment digit 5[0] depending on jp6 hex5[1] pin_ac18 seven segment digit 5[1] depending on jp6 hex5[2] pin_ab18 seven segment digit 5[2] depending on jp6 hex5[3] pin_ah19 seven segment digit 5[3] depending on jp6 hex5[4] pin_ag19 seven segment digit 5[4] depending on jp6 hex5[5] pin_af18 seven segment digit 5[5] depending on jp6 hex5[6] pin_ah18 seven segment digit 5[6] depending on jp6 hex6[0] pin_aa17 seven segment digit 6[0] depending on jp6 hex6[1] pin_ab16 seven segment digit 6[1] depending on jp6 hex6[2] pin_aa16 seven segment digit 6[2] depending on jp6 hex6[3] pin_ab17 seven segment digit 6[3] depending on jp6 hex6[4] pin_ab15 seven segment digit 6[4] depending on jp6 hex6[5] pin_aa15 seven segment digit 6[5] depending on jp6 hex6[6] pin_ac17 seven segment digit 6[6] depending on jp6 hex7[0] pin_ad17 seven segment digit 7[0] depending on jp6 hex7[1] pin_ae17 seven segment digit 7[1] depending on jp6 38 hex7[2] pin_ag17 seven segment digit 7[2] depending on jp6 hex7[3] pin_ah17 seven segment digit 7[3] depending on jp6 hex7[4] pin_af17 seven segment digit 7[4] depending on jp6 hex7[5] pin_ag18 seven segment digit 7[5] depending on jp6 hex7[6] pin_aa14 seven se gment digit 7[6] 3.3v 4 4 . . 5 5 c c l l o o c c k k c c i i r r c c u u i i t t r r y y the de2-115 board includes one oscillator that produces 50 mhz clock signal. a clock buffer is used to distribute 50 mhz clock si gnal with low jitter to fpga. th e distributing clock signals are connected to the fpga that are used for clocking the user logic. the board also includes two sma connectors which can be used to connect an extern al clock source to the boa rd or to drive a clock signal out through the sma connector. in addition, all these clock inpu ts are connected to the phase locked loops (pll) clock input pins of the fpga to allow users to use these clocks as a source clock for the pll circuit. the clock distribution on the de2-115 board is shown in figure 4-11 . the associa ted pin assignments for clock inputs to fpga i/o pins are listed in table 4-5 . figure 4-11 block diagram of the clock distribution table 4-5 pin assignments for clock inputs signal name fpga pin no. description i/o standard clock_50 pin_y2 50 mhz clock input 3.3v clock2_50 pin_ag14 50 mhz clock input 3.3v clock3_50 pin_ag15 50 mhz clock input depending on jp6 sma_clkout pin_ae23 external (sma) clock output depending on jp6 sma_clkin pin_ah14 external (sma) clock input 3.3v 39 4 4 . . 6 6 u u s s i i n n g g t t h h e e l l c c d d m m o o d d u u l l e e the lcd module has built-in font s and can be used to display text by sending appropriate commands to the display controll er called hd44780. detailed informa tion for using the display is available in its datasheet, which can be foun d on the manufacturer?s website, and from the de2_115_datasheets\lcd folder on the de2-115 system cd . a schematic diagram of the lcd module showing connections to the cyclone iv e fpga is given in figure 4-12 . the associated p in assignments appear in table 4-6 . figure 4-12 connections between the lcd module and cyclone iv e fpga *(1): note the current lcd modules used on de2-115 boards do not have backlight. therefore the lcd_blon signal should not be used in users? design projects. table 4-6 pin assignments for lcd module signal name fpga pin no. description i/o standard lcd_data[7] pin_m5 lcd data[7] 3.3v lcd_data[6] pin_m3 lcd data[6] 3.3v lcd_data[5] pin_k2 lcd data[5] 3.3v lcd_data[4] pin_k1 lcd data[4] 3.3v lcd_data[3] pin_k7 lcd data[3] 3.3v 40 lcd_data[2] pin_l2 lcd data[2] 3.3v lcd_data[1] pin_l1 lcd data[1] 3.3v lcd_data[0] pin_l3 lcd data[0] 3.3v lcd_en pin_l4 lcd enable 3.3v lcd_rw pin_m1 lcd read/write select, 0 = write, 1 = read 3.3v lcd_rs pin_m2 lcd command/data select, 0 = command, 1 = data 3.3v lcd_on pin_l5 lcd power on/off 3.3v lcd_blon pin_l6 lcd back light on/off 3.3v 4 4 . . 7 7 h h i i g g h h s s p p e e e e d d m m e e z z z z a a n n i i n n e e c c a a r r d d the de2-115 development board contains a hsmc interface to provide a mechanism for extending the peripheral-set of a fpga host board by means of add-on cards. this can address today?s high speed signaling requirement as well as low-speed device interface support. the hsmc interface support jtag, clock outputs and inputs, high speed lvds and single-ended signaling. the hsmc connector connects directly to th e cyclone iv e fpga with 82 pins. signals hsmc_sda and hsmc_sclk share the same bus with the resp ected signals i2c_sda and i2c_scl of the wm8731 audio ship and adv7180 tv decoder chip. table 4-7 shows the m aximum power consumption of the daughter card that connects to hsmc port. table 4-7 power supply of the hsmc supplied voltage max. current limit 12v 1a 3.3v 1.5a (1).note the current levels indicated in table 4-7 ar e based on 50% resource consumption. if the hsmc interface is utilized with design resources ex ceeding 50%, please notify our support ( support@terasic.com ). (2).if the hsmc loopback adapter is mounted, th e i2c_scl will be directly routed back to i2c_sda. because audio chip, tv decoder chip and hsmc share one i2c bus, therefore audio and video chip won?t function correctly. the voltage level of the i/o pins on the hsmc connector can be adjusted to 3.3v, 2.5v, 1.8v, or 1.5v using jp7 (the default setting is 2.5v, see figure 4-13 ). because the h smc i/os are connected to bank 5 & 6 of the fpga and th e vccio voltage (vccio5 & vccio6) of these banks are controlled by the header jp7, users can use a jumper to select the input voltage of vccio5 & vccio6 to 3.3v, 2.5v, 1.8v, and 1.5v to control the voltage le vel of the i/o pins. table 4-8 lists the jum per settings of the jp7. 41 figure 4-13 hsmc vccio supply voltage setting header table 4-8 jumper settings for different i/o standards jp7 jumper settings supplied voltage to vccio5 & vccio6 io voltage of hsmc connector (jp8) short pins 1 and 2 1.5v 1.5v short pins 3 and 4 1.8v 1.8v short pins 5 and 6 2.5v 2.5v (default) short pins 7 and 8 3.3v 3.3v note: users that connect a daughter card on the hsmc connector need to pay close attention on the i/o standard between de2-115 hs mc connector pins and daughter card system. for example, if the i/o standard of hsmc pins on de2-115 board is set to 1.8v, a daughter card with 3.3v i/o standard may not work properly on de2-115 board due to i/o standard mismatch. additionally, when lvds is used as the i/o stan dard of the hsmc connector, the lvds receivers need to assemble a 100 ohm resistor between two input signals for each pairs as shown in figure 4-14. table 4-9 shows all the pin assignm ents of the hsmc connector. 42 figure 4-14 lvds interface on hsmc connector and cyclone iv e fpga table 4-9 pin assignments for hsmc connector signal name fpga pin no. description i/o standard hsmc_clkin0 pin_ah15 dedicated clock input depending on jp6 hsmc_clkin_n1 pin_j28 lvds rx or cmos i/o or differential clock input depending on jp7 hsmc_clkin_n2 pin_y28 lvds rx or cmos i/o or differential clock input depending on jp7 hsmc_clkin_p1 pin_j27 lvds rx or cmos i/o or differential clock input depending on jp7 hsmc_clkin_p2 pin_y27 lvds rx or cmos i/o or differential clock input depending on jp7 hsmc_clkout0 pin_ad28 dedicated clock output depending on jp7 hsmc_clkout_n1 pin_g24 lvds tx or cmos i/o or differential clock input/output depending on jp7 hsmc_clkout_n2 pin_v24 lvds tx or cmos i/o or differential clock input/output depending on jp7 hsmc_clkout_p1 pin_g23 lvds tx or cmos i/o or differential clock input/output depending on jp7 hsmc_clkout_p2 pin_v23 lvds tx or cmos i/o or differential clock input/output depending on jp7 hsmc_d[0] pin_ae26 lvds tx or cmos i/o depending on jp7 hsmc_d[1] pin_ae28 lvds rx or cmos i/o depending on jp7 hsmc_d[2] pin_ae27 lvds tx or cmos i/o depending on jp7 hsmc_d[3] pin_af27 lvds rx or cmos i/o depending on jp7 hsmc_rx_d_n[0] pin_f25 lvds rx bit 0n or cmos i/o depending 43 on jp7 hsmc_rx_d_n[1] pin_c27 lvds rx bit 1n or cmos i/o depending on jp7 hsmc_rx_d_n[2] pin_e26 lvds rx bit 2n or cmos i/o depending on jp7 hsmc_rx_d_n[3] pin_g26 lvds rx bit 3n or cmos i/o depending on jp7 hsmc_rx_d_n[4] pin_h26 lvds rx bit 4n or cmos i/o depending on jp7 hsmc_rx_d_n[5] pin_k26 lvds rx bit 5n or cmos i/o depending on jp7 hsmc_rx_d_n[6] pin_l24 lvds rx bit 6n or cmos i/o depending on jp7 hsmc_rx_d_n[7] pin_m26 lvds rx bit 7n or cmos i/o depending on jp7 hsmc_rx_d_n[8] pin_r26 lvds rx bit 8n or cmos i/o depending on jp7 hsmc_rx_d_n[9] pin_t26 lvds rx bit 9n or cmos i/o depending on jp7 hsmc_rx_d_n[10] pin_u26 lvds rx bit 10n or cmos i/o depending on jp7 hsmc_rx_d_n[11] pin_l22 lvds rx bit 11n or cmos i/o depending on jp7 hsmc_rx_d_n[12] pin_n26 lvds rx bit 12n or cmos i/o depending on jp7 hsmc_rx_d_n[13] pin_p26 lvds rx bit 13n or cmos i/o depending on jp7 hsmc_rx_d_n[14] pin_r21 lvds rx bit 14n or cmos i/o depending on jp7 hsmc_rx_d_n[15] pin_r23 lvds rx bit 15n or cmos i/o depending on jp7 hsmc_rx_d_n[16] pin_t22 lvds rx bit 16n or cmos i/o depending on jp7 hsmc_rx_d_p[0] pin_f24 lvds rx bit 0 or cmos i/o depending on jp7 hsmc_rx_d_p[1] pin_d26 lvds rx bit 1 or cmos i/o depending on jp7 hsmc_rx_d_p[2] pin_f26 lvds rx bit 2 or cmos i/o depending on jp7 hsmc_rx_d_p[3] pin_g25 lvds rx bit 3 or cmos i/o depending on jp7 hsmc_rx_d_p[4] pin_h25 lvds rx bit 4 or cmos i/o depending on jp7 hsmc_rx_d_p[5] pin_k25 lvds rx bit 5 or cmos i/o depending on jp7 hsmc_rx_d_p[6] pin_l23 lvds rx bit 6 or cmos i/o depending on jp7 44 hsmc_rx_d_p[7] pin_m25 lvds rx bit 7 or cmos i/o depending on jp7 hsmc_rx_d_p[8] pin_r25 lvds rx bit 8 or cmos i/o depending on jp7 hsmc_rx_d_p[9] pin_t25 lvds rx bit 9 or cmos i/o depending on jp7 hsmc_rx_d_p[10] pin_u25 lvds rx bit 10 or cmos i/o depending on jp7 hsmc_rx_d_p[11] pin_l21 lvds rx bit 11 or cmos i/o depending on jp7 hsmc_rx_d_p[12] pin_n25 lvds rx bit 12 or cmos i/o depending on jp7 hsmc_rx_d_p[13] pin_p25 lvds rx bit 13 or cmos i/o depending on jp7 hsmc_rx_d_p[14] pin_p21 lvds rx bit 14 or cmos i/o depending on jp7 hsmc_rx_d_p[15] pin_r22 lvds rx bit 15 or cmos i/o depending on jp7 hsmc_rx_d_p[16] pin_t21 lvds rx bit 16 or cmos i/o depending on jp7 hsmc_tx_d_n[0] pin_d28 lvds tx bit 0n or cmos i/o depending on jp7 hsmc_tx_d_n[1] pin_e28 lvds tx bit 1n or cmos i/o depending on jp7 hsmc_tx_d_n[2] pin_f28 lvds tx bit 2n or cmos i/o depending on jp7 hsmc_tx_d_n[3] pin_g28 lvds tx bit 3n or cmos i/o depending on jp7 hsmc_tx_d_n[4] pin_k28 lvds tx bit 4n or cmos i/o depending on jp7 hsmc_tx_d_n[5] pin_m28 lvds tx bit 5n or cmos i/o depending on jp7 hsmc_tx_d_n[6] pin_k22 lvds tx bit 6n or cmos i/o depending on jp7 hsmc_tx_d_n[7] pin_h24 lvds tx bit 7n or cmos i/o depending on jp7 hsmc_tx_d_n[8] pin_j24 lvds tx bit 8n or cmos i/o depending on jp7 hsmc_tx_d_n[9] pin_p28 lvds tx bit 9n or cmos i/o depending on jp7 hsmc_tx_d_n[10] pin_j26 lvds tx bit 10n or cmos i/o depending on jp7 hsmc_tx_d_n[11] pin_l28 lvds tx bit 11n or cmos i/o depending on jp7 hsmc_tx_d_n[12] pin_v26 lvds tx bit 12n or cmos i/o depending on jp7 hsmc_tx_d_n[13] pin_r28 lvds tx bit 13n or cmos i/o depending 45 on jp7 hsmc_tx_d_n[14] pin_u28 lvds tx bit 14n or cmos i/o depending on jp7 hsmc_tx_d_n[15] pin_v28 lvds tx bit 15n or cmos i/o depending on jp7 hsmc_tx_d_n[16] pin_v22 lvds tx bit 16n or cmos i/o depending on jp7 hsmc_tx_d_p[0] pin_d27 lvds tx bit 0 or cmos i/o depending on jp7 hsmc_tx_d_p[1] pin_e27 lvds tx bit 1 or cmos i/o depending on jp7 hsmc_tx_d_p[2] pin_f27 lvds tx bit 2 or cmos i/o depending on jp7 hsmc_tx_d_p[3] pin_g27 lvds tx bit 3 or cmos i/o depending on jp7 hsmc_tx_d_p[4] pin_k27 lvds tx bit 4 or cmos i/o depending on jp7 hsmc_tx_d_p[5] pin_m27 lvds tx bit 5 or cmos i/o depending on jp7 hsmc_tx_d_p[6] pin_k21 lvds tx bit 6 or cmos i/o depending on jp7 hsmc_tx_d_p[7] pin_h23 lvds tx bit 7 or cmos i/o depending on jp7 hsmc_tx_d_p[8] pin_j23 lvds tx bit 8 or cmos i/o depending on jp7 hsmc_tx_d_p[9] pin_p27 lvds tx bit 9 or cmos i/o depending on jp7 hsmc_tx_d_p[10] pin_j25 lvds tx bit 10 or cmos i/o depending on jp7 hsmc_tx_d_p[11] pin_l27 lvds tx bit 11 or cmos i/o depending on jp7 hsmc_tx_d_p[12] pin_v25 lvds tx bit 12 or cmos i/o depending on jp7 hsmc_tx_d_p[13] pin_r27 lvds tx bit 13 or cmos i/o depending on jp7 hsmc_tx_d_p[14] pin_u27 lvds tx bit 14 or cmos i/o depending on jp7 hsmc_tx_d_p[15] pin_v27 lvds tx bit 15 or cmos i/o depending on jp7 hsmc_tx_d_p[16] pin_u22 lvds tx bit 16 or cmos i/o depending on jp7 4 4 . . 8 8 u u s s i i n n g g t t h h e e e e x x p p a a n n s s i i o o n n h h e e a a d d e e r r the de2-115 board provides one 40-pin expansion h eader. the header connects directly to 36 pins of the cyclone iv e fpga, and also provides dc +5v (vcc5), dc +3.3v (vcc3p3), and two 46 gnd pins. figure 4-15 shows the i/o distribution of the gpio connector . the maximum power consumption of the daughter card that connects to gpio port is shown in table 4-10 . figure 4-15 gpio pin arrangement table 4-10 power supply of the expansion header supplied voltage max. current limit 5v 1a 3.3v 1.5a each pin on the expansion headers is connected to two diodes and a re sistor that prov ides protection against high and low voltages. figure 4-16 show s the protection circuitr y for only one of the pin on the header, but this circuitry is included for all 36 data pins. figure 4-16 connections between the gpio connector and cyclone iv e fpga 47 the voltage level of the i/o pins on the expansi on headers can be adjusted to 3.3v, 2.5v, 1.8v, or 1.5v using jp6 (the default value is 3.3v, see figure 4-17 ). becaus e the expansion i/os are connected to bank 4 of the fpga and the vccio voltage (vccio4) of this bank is controlled by the header jp6, users can use a ju mper to select the input voltage of vccio4 to 3.3v, 2.5v, 1.8v, and 1.5v to control the volta ge level of the i/o pins. table 4-11 lists the jum per settings of the jp6. the pin-outs of the jp6 appear in figure 4-17 . figure 4-17 gpio vccio supply voltage setting header table 4-11 voltage level setting of the expansion headers using jp6 jp6 jumper settings supplied voltage to vccio4 io voltage of expansion headers (jp5) short pins 1 and 2 1.5v 1.5v short pins 3 and 4 1.8v 1.8v short pins 5 and 6 2.5v 2.5v short pins 7 and 8 3.3v 3.3v (default) 48 note : users who want to use daughter card on gpio connector need to pay close attention to the i/o standard between de2-115 gpio co nnector pins and daughter card system. for example, if the i/o standard of gpio pins on de2-115 board is se t to 1.8v, a daughter card with 3.3v i/o standard may not work properly on th e de2-115 board due to i/o standard mismatch. figure 4-18 depicts the pin definition on the expansion connector for using these i/os as l vds transmitters. due to the reason that the column i/os of the fpga the expansion pins connecting with can only support emulated lvds transmitters, two single-ended output buffers and external resistors must be used as shown in figure 4-19 . the associated i/o standard of these dif ferential fpga i/o pins on quartus ii proj ect should set to lvds_e_3r. figure 4-18 pin defined when using lvds interface on gpio fpga pins the factory default setting on rs re sistor will be 47 ohm and rp resi stor will not be assembled for single-ended i/o standard application. for lvds transmitter application, please assemble 120 and 170 ohm resistor on rs and rp position, respectively. finally, table 4-12 shows all the pin assignm ents of the gpio connector. 49 figure 4-19 using emulated lvds on gpio table 4-12 pin assignments for expansion headers signal name fpga pin no. description i/o standard gpio[0] pin_ab22 gpio connection data[0] depending on jp6 gpio[1] pin_ac15 gpio connection data[1] depending on jp6 gpio[2] pin_ab21 gpio connection data[2] depending on jp6 gpio[3] pin_y17 gpio connection data[3] depending on jp6 gpio[4] pin_ac21 gpio connection data[4] depending on jp6 gpio[5] pin_y16 gpio connection data[5] depending on jp6 gpio[6] pin_ad21 gpio connection data[6] depending on jp6 gpio[7] pin_ae16 gpio connection data[7] depending on jp6 gpio[8] pin_ad15 gpio connection data[8] depending on jp6 gpio[9] pin_ae15 gpio connection data[9] depending on jp6 gpio[10] pin_ac19 gpio connection data[10] depending on jp6 gpio[11] pin_af16 gpio connection data[11] depending on jp6 gpio[12] pin_ad19 gpio connection data[12] depending on jp6 gpio[13] pin_af15 gpio connection data[13] depending on jp6 gpio[14] pin_af24 gpio connection data[14] depending on jp6 gpio[15] pin_ae21 gpio connection data[15] depending on jp6 gpio[16] pin_af25 gpio connection data[16] depending on jp6 gpio[17] pin_ac22 gpio connection data[17] depending on jp6 gpio[18] pin_ae22 gpio connection data[18] depending on jp6 gpio[19] pin_af21 gpio connection data[19] depending on jp6 gpio[20] pin_af22 gpio connection data[20] depending on jp6 gpio[21] pin_ad22 gpio connection data[21] depending on jp6 gpio[22] pin_ag25 gpio connection data[22] depending on jp6 gpio[23] pin_ad25 gpio connection data[23] depending on jp6 gpio[24] pin_ah25 gpio connection data[24] depending on jp6 gpio[25] pin_ae25 gpio connection data[25] depending on jp6 gpio[26] pin_ag22 gpio connection data[26] depending on jp6 gpio[27] pin_ae24 gpio connection data[27] depending on jp6 gpio[28] pin_ah22 gpio connection data[28] depending on jp6 50 gpio[29] pin_af26 gpio connection data[29] depending on jp6 gpio[30] pin_ae20 gpio connection data[30] depending on jp6 gpio[31] pin_ag23 gpio connection data[31] depending on jp6 gpio[32] pin_af20 gpio connection data[32] depending on jp6 gpio[33] pin_ah26 gpio connection data[33] depending on jp6 gpio[34] pin_ah23 gpio connection data[34] depending on jp6 gpio[35] pin_ag26 gpio connection data[35] depending on jp6 4 4 . . 9 9 u u s s i i n n g g 1 1 4 4 - - p p i i n n g g e e n n e e r r a a l l p p u u r r p p o o s s e e i i / / o o c c o o n n n n e e c c t t o o r r the de2-115 board provides 14-pin expansion header. the h eader connects directly to 7 pins of the cyclone iv e fpga, and also provides dc + 3.3v (vcc3p3), and six gnd pins as shown in figure 4-20 . the voltage level of the i/o pins on th e 14-pin expansion header is 3.3v . finally, table 4-13 shows the pin assignm ents for i/o connections. figure 4-20 connections between fpga and 14-pin general purpose i/o table 4-13 pin assignments for general purpose i/os signal name fpga pin no. description i/o standard ex_io[0] pin_j10 extended io[0] 3.3v ex_io[1] pin_j14 extended io[1] 3.3v ex_io[2] pin_h13 extended io[2] 3.3v ex_io[3] pin_h14 extended io[3] 3.3v ex_io[4] pin_f14 extended io[4] 3.3v ex_io[5] pin_e10 extended io[5] 3.3v ex_io[6] pin_d9 extended io[6] 3.3v 51 4 4 . . 1 1 0 0 u u s s i i n n g g v v g g a a the de2-115 board includes a 15-pin d-sub conn ector for vga output. th e vga synchronization signals are provided directly from the cycl one iv e fpga, and th e analog devices adv7123 triple 10-bit high-speed video dac (only the higher 8-bits are used) is used to produce the analog data signals (red, green, and blue). it coul d support the sxga stan dard (1280*1024) with a bandwidth of 100mhz. figure 4-21 gives the associated schem atic. figure 4-21 connections between fpga and vga the timing specification for vga synchronization and rg b (red, green, blue) data can be found on various educational website (for example, search for ?vga signal timing?). figure 4-22 illus trates the basic timing requirements for each row (horizon tal) that is displayed on a vga monitor. an active-low pulse of specific duration (time (a) in the figure) is app lied to the horizontal synchronization (hsync) input of the monitor, whic h signifies the end of one row of data and the start of the next. the data (rgb) output to the monitor must be off (driven to 0 v) for a time period called the back porch (b) after the hsync pulse occu rs, which is followed by th e display interval (c). during the data display interval the rgb data drives each pixel in turn across the row being displayed. finally, there is a time period called the front porch (d) where the rgb signals must again be off before the next hsync pulse can o ccur. the timing of the vertical synchronization (vsync) is the similar as shown in figure 4-22 , except that a vsync pulse signifies the end of one frame and the start of the next, and the data refers to the set of rows in the frame (horizontal timing). table 4-14 and table 4-15 show dif ferent resolutions and durations of time periods a, b, c, and d for both horizontal a nd vertical timing. detailed information for using the adv7123 video dac is available in its datasheet, which can be found on the manufacturer?s website, or in the de2_115_datasheets\video-dac folder on the de2-115 system cd. the pin assignments between the cyclone iv e fpga and the adv7123 are listed in table 4-16 . an exam ple of code that drives a vga display is described in sections 6.2 and 6.3. 52 note: the rgb data bus on de2-115 board is 8 bit instead of 10 bit on de2/de2-70 board. figure 4-22 vga horizontal timing specification table 4-14 vga horizontal timing specification vga mode horizontal timing spec configuration resolution(hxv) a(us) b(us) c(us) d(us) pixel clock(mhz) vga(60hz) 640x480 3.8 1.9 25.4 0.6 25 vga(85hz) 640x480 1.6 2.2 17.8 1.6 36 svga(60hz) 800x600 3.2 2.2 20 1 40 svga(75hz) 800x600 1.6 3.2 16.2 0.3 49 svga(85hz) 800x600 1.1 2.7 14.2 0.6 56 xga(60hz) 1024x768 2.1 2.5 15.8 0.4 65 xga(70hz) 1024x768 1.8 1.9 13.7 0.3 75 xga(85hz) 1024x768 1.0 2.2 10.8 0.5 95 1280x1024(60hz) 1280x1024 1.0 2.3 11.9 0.4 108 table 4-15 vga vertical timing specification vga mode vertical timing spec configuration resolution(hxv) a(lines) b(lines) c(lines) d(lines) pixel clock(mhz) vga(60hz) 640x480 2 33 480 10 25 vga(85hz) 640x480 3 25 480 1 36 svga(60hz) 800x600 4 23 600 1 40 svga(75hz) 800x600 3 21 600 1 49 svga(85hz) 800x600 3 27 600 1 56 xga(60hz) 1024x768 6 29 768 3 65 xga(70hz) 1024x768 6 29 768 3 75 xga(85hz) 1024x768 3 36 768 1 95 1280x1024(60hz) 1280x1024 3 38 1024 1 108 53 table 4-16 pin assignments for adv7123 signal name fpga pin no. description i/o standard vga_r[0] pin_e12 vga red[0] 3.3v vga_r[1] pin_e11 vga red[1] 3.3v vga_r[2] pin_d10 vga red[2] 3.3v vga_r[3] pin_f12 vga red[3] 3.3v vga_r[4] pin_g10 vga red[4] 3.3v vga_r[5] pin_j12 vga red[5] 3.3v vga_r[6] pin_h8 vga red[6] 3.3v vga_r[7] pin_h10 vga red[7] 3.3v vga_g[0] pin_g8 vga green[0] 3.3v vga_g[1] pin_g11 vga green[1] 3.3v vga_g[2] pin_f8 vga green[2] 3.3v vga_g[3] pin_h12 vga green[3] 3.3v vga_g[4] pin_c8 vga green[4] 3.3v vga_g[5] pin_b8 vga green[5] 3.3v vga_g[6] pin_f10 vga green[6] 3.3v vga_g[7] pin_c9 vga green[7] 3.3v vga_b[0] pin_b10 vga blue[0] 3.3v vga_b[1] pin_a10 vga blue[1] 3.3v vga_b[2] pin_c11 vga blue[2] 3.3v vga_b[3] pin_b11 vga blue[3] 3.3v vga_b[4] pin_a11 vga blue[4] 3.3v vga_b[5] pin_c12 vga blue[5] 3.3v vga_b[6] pin_d11 vga blue[6] 3.3v vga_b[7] pin_d12 vga blue[7] 3.3v vga_clk pin_a12 vga clock 3.3v vga_blank_n pin_f11 vga blank 3.3v vga_hs pin_g13 vga h_sync 3.3v vga_vs pin_c13 vga v_sync 3.3v vga_sync_n pin_c1 0 vga sync 3.3v 4 4 . . 1 1 1 1 u u s s i i n n g g t t h h e e 2 2 4 4 - - b b i i t t a a u u d d i i o o c c o o d d e e c c the de2-115 board provides high-quality 24- bit audio via the wolf son wm8731 audio codec (encoder/decoder). this chip supports microphone-in, li ne-in, and line-out ports, with a sample rate adjustable from 8 khz to 96 khz. the wm8731 is c ontrolled via serial i2c bus interface*, which is connected to pins on the cyclone iv e fpga. a sc hematic diagram of the audio circuitry is shown in figure 4-23 , and the fpga pin assignments are listed in table 4-17 . detailed inf ormation for using the wm8731 codec is available in its data sheet, which can be found on the manufacturer?s website, or in the de2_115_datasheets\audio codec folder on the de2-115 system cd. 54 figure 4-23 connections between fpga and audio codec table 4-17 audio codec pin assignments signal name fpga pin no. description i/o standard aud_adclrck pin_c2 audio codec adc lr clock 3.3v aud_adcdat pin_d2 audio codec adc data 3.3v aud_daclrck pin_e3 audio codec dac lr clock 3.3v aud_dacdat pin_d1 audio codec dac data 3.3v aud_xck pin_e1 audio codec chip clock 3.3v aud_bclk pin_f2 audio codec bit-stream clock 3.3v i2c_sclk pin_b7 i2c clock 3.3v i2c_sdat pin_a8 i2c data 3.3v note: if the hsmc loopback adapter is mounted, the i2c_scl will be directly routed back to i2c_sda. because audio chip, tv decoder chip and hsmc share one i2c bus, therefore audio and video chip won?t function correctly. 4 4 . . 1 1 2 2 r r s s - - 2 2 3 3 2 2 s s e e r r i i a a l l p p o o r r t t the de2-115 board uses the zt3232 transceiver chip and a 9-pin db9 connector for rs-232 communications. for detailed information on how to use the transceiver, please refer to the datasheet, which is available on the manufacturer?s website, or in the de2_115_datasheets\rs-232 folder on the de2-115 system cd. figure 4-24 shows the related schem atics, and table 4-18 lists the cyclone iv e fpga pin assignments. 55 figure 4-24 connections between fpga and zt3232 (rs-232) chip table 4-18 rs-232 pin assignments signal name fpga pin no. description i/o standard uart_rxd pin_g12 uart receiver 3.3v uart_txd pin_g9 uart transmitter 3.3v uart_cts pin_g14 uart clear to send 3.3v uart_rts pin_j13 uart request to send 3.3v 4 4 . . 1 1 3 3 p p s s / / 2 2 s s e e r r i i a a l l p p o o r r t t the de2-115 board includes a standard ps/2 inte rface and a connector for a ps/2 keyboard or mouse. figure 4-25 shows the schem atic of the ps/2 circuit. in addition, users can use the ps/2 keyboard and mouse on the de2-115 board simulta neously by plugging an extension ps/2 y-cable (see figure 4-26 ). instructions for using a ps/2 mouse or keyboard can be found by perform ing an appropriate search on various educational websites . the pin assignments for the associated interface are shown in table 4-19 . note: if users connect only one ps/2 equipm ent, the ps/2 interface between fpga i/o should be ?ps2_clk? and ?ps2_dat? . figure 4-25 connection between fpga and ps/2 56 figure 4-26 y-cable use for both keyboard and mouse table 4-19 ps/2 pin assignments signal name fpga pin no. description i/o standard ps2_clk pin_g6 ps/2 clock 3.3v ps2_dat pin_h5 ps/2 data 3.3v ps2_clk2 pin_g5 ps/2 clock (reserved for second ps/2 device) 3.3v ps2_dat2 pin_f5 ps/2 data (reserved for second ps/2 device) 3.3v 4 4 . . 1 1 4 4 g g i i g g a a b b i i t t e e t t h h e e r r n n e e t t t t r r a a n n s s c c e e i i v v e e r r the de2-115 board provides ethe rnet support via two marvell 88e 1111 ethernet phy chips. the 88e1111 chip with integrated 10/ 100/1000 mbps gigabit ethern et transceiver support gmii/mii/rgmii/tbi mac interfaces. table 4-20 describes the default settings for both chips. figure 4-27 shows the connection setup between the gigabit ethern et phy (enet0) and fpga. table 4-20 default configuration for gigabit ethernet configuration description default value phyaddr[4:0] phy address in mdio/m dc mode 10000 for enet0;10001 for enet1 ena_pause enable pause 1-default register 4.11:10 to 11 aneg[3:0] auto negotiation configuration for copper modes 1110-auto-neg, advertise all capabilities, prefer master ena_xc enable crossover 0-disable dis_125 disable 125mhz clock 1-disable 125clk hwcfg[3:0] hardware configuration mode 1011/1111 rgmii to copper/gmii to copper dis_fc disable fiber/copper interface 1-disable dis_sleep energy detect 1-disable energy detect sel_twsi interface select 0-select mdc/mdio interface int_pol interrupt polarity 1- intn signal is active low 75/50ohm termination resistance 0-50 ohm termination for fiber here only rgmii and mii modes are supported on th e board (the factory de fault mode is rgmii). there is one jumper for each chip for swit ching work modes from rgmii to mii (see figure 4-28 ). 57 you will need to perform a hardware reset after any change for enabling new settings. table 4-21 and table 4-22 describe the working m ode settings fo r enet0 phy (u8) and enet1 phy (u9) respectively. in addition, it is dynamically configurable to support 10mbps , 100mbps (fast ethernet) or 1000mbps (gigabit ethernet) operation using standa rd cat 5e utp cabling. the associated pin assignments are listed in table 4-23 . for detailed information on how to use the 88e1111 refers to its datasheet and application notes, which ar e available on the manufacturer?s website. figure 4-27 connections between fpga and ethernet figure 4-28 working mode setup header for ethernet phy table 4-21 jumper settings for working mode of enet0 (u8) jp1 jumper settings enet0 phy working mode short pins 1 and 2 rgmii mode short pins 2 and 3 mii mode 58 table 4-22 jumper settings for working mode of enet1 (u9) jp2 jumper settings enet1 phy working mode short pins 1 and 2 rgmii mode short pins 2 and 3 mii mode table 4-23 pin assignments for fast ethernet signal name fpga pin no. description i/o standard enet0_gtx_clk pin_a17 gmii transmit clock 1 2.5v enet0_int_n pin_a21 interrupt open drain output 1 2.5v enet0_link100 pin_c14 parallel led output of 100base-tx link 1 3.3v enet0_mdc pin_c20 management data clock reference 1 2.5v enet0_mdio pin_b21 management data 1 2.5v enet0_rst_n pin_c19 hardware reset signal 1 2.5v enet0_rx_clk pin_a15 gmii and mii receive clock 1 2.5v enet0_rx_col pin_e15 gmii and mii collision 1 2.5v enet0_rx_crs pin_d15 gmii and mii carrier sense 1 2.5v enet0_rx_data[0] pin_c16 gmii and mii receive data[0] 1 2.5v enet0_rx_data[1] pin_d16 gmii and mii receive data[1] 1 2.5v enet0_rx_data[2] pin_d17 gmii and mii receive data[2] 1 2.5v enet0_rx_data[3] pin_c15 gmii and mii receive data[3] 1 2.5v enet0_rx_dv pin_c17 gmii and mii receive data valid 1 2.5v enet0_rx_er pin_d18 gmii and mii receive error 1 2.5v enet0_tx_clk pin_b17 mii transmit clock 1 2.5v enet0_tx_data[0] pin_c18 mii transmit data[0] 1 2.5v enet0_tx_data[1] pin_d19 mii transmit data[1] 1 2.5v enet0_tx_data[2] pin_a19 mii transmit data[2] 1 2.5v enet0_tx_data[3] pin_b19 mii transmit data[3] 1 2.5v enet0_tx_en pin_a18 gmii and mii transmit enable 1 2.5v enet0_tx_er pin_b18 gmii and mii transmit error 1 2.5v enet1_gtx_clk pin_c23 gmii transmit clock 2 2.5v enet1_int_n pin_d24 interrupt open drain output 2 2.5v enet1_link100 pin_d13 parallel led output of 100base-tx link 2 3.3v enet1_mdc pin_d23 management data clock reference 2 2.5v enet1_mdio pin_d25 management data 2 2.5v enet1_rst_n pin_d22 hardware reset signal 2 2.5v enet1_rx_clk pin_b15 gmii and mii receive clock 2 2.5v enet1_rx_col pin_b22 gmii and mii collision 2 2.5v enet1_rx_crs pin_d20 gmii and mii carrier sense 2 2.5v enet1_rx_data[0] pin_b23 gmii and mii receive data[0] 2 2.5v enet1_rx_data[1] pin_c21 gmii and mii receive data[1] 2 2.5v enet1_rx_data[2] pin_a23 gmii and mii receive data[2] 2 2.5v enet1_rx_data[3] pin_d21 gmii and mii receive data[3] 2 2.5v enet1_rx_dv pin_a22 gmii and mii receive data valid 2 2.5v enet1_rx_er pin_c24 gmii and mii receive error 2 2.5v 59 enet1_tx_clk pin_c22 mii transmit clock 2 2.5v enet1_tx_data[0] pin_c25 mii transmit data[0] 2 2.5v enet1_tx_data[1] pin_a26 mii transmit data[1] 2 2.5v enet1_tx_data[2] pin_b26 mii transmit data[2] 2 2.5v enet1_tx_data[3] pin_c26 mii transmit data[3] 2 2.5v enet1_tx_en pin_b25 gmii and mii transmit enable 2 2.5v enet1_tx_er pin_a25 gmii and mii transmit error 2 2.5v enetclk_25 pin_a14 ethernet clock source 3.3v 4 4 . . 1 1 5 5 t t v v d d e e c c o o d d e e r r the de2-115 board is equipped with an anal og device adv7180 tv dec oder chip. the adv7180 is an integrated video decoder that automatically detects and converts a st andard analog baseband television signals (ntsc, pal, and secam) into 4:2:2 component video data compatible with the 8-bit itu-r bt.656 interface standard. the adv7180 is compatible with a broad range of video devices, including dvd players, tape-based sources, broadcast sources, and security/surveillance cameras. the registers in the tv decoder can be programmed by a serial i2c bus, which is connected to the cyclone iv e fpga as indicated in figure 4-29 . note th at the i2c address w/r of the tv decoder (u6) is 0x40/0x41. the pin assignments are listed in table 4-24 . detailed inform ation of the adv7180 is available on the manufacturer?s website, or in the de2_115_datasheets\tv decoder folder on the de2-115 system cd. figure 4-29 connections between fpga and tv decoder 60 note: if the hsmc loopback adapter is mounted, the i2c_scl will be directly routed back to i2c_sda. because audio chip, tv decoder chip and hsmc share one i2c bus, therefore audio and video chip won?t function correctly. table 4-24 tv decoder pin assignments signal name fpga pin no. description i/o standard td_ data [0] pin_e8 tv decoder data[0] 3.3v td_ data [1] pin_a7 tv decoder data[1] 3.3v td_ data [2] pin_d8 tv decoder data[2] 3.3v td_ data [3] pin_c7 tv decoder data[3] 3.3v td_ data [4] pin_d7 tv decoder data[4] 3.3v td_ data [5] pin_d6 tv decoder data[5] 3.3v td_ data [6] pin_e7 tv decoder data[6] 3.3v td_ data [7] pin_f7 tv decoder data[7] 3.3v td_hs pin_e5 tv decoder h_sync 3.3v td_vs pin_e4 tv decoder v_sync 3.3v td_clk27 pin_b14 tv decoder clock input. 3.3v td_reset_n pin_g7 tv decoder reset 3.3v i2c_sclk pin_b7 i2c clock 3.3v i2c_sdat pin_a8 i2c data 3.3v 4 4 . . 1 1 6 6 i i m m p p l l e e m m e e n n t t i i n n g g a a t t v v e e n n c c o o d d e e r r although the de2-115 board does not include a tv encoder chip, the adv7123 (10-bit high-speed triple adcs) can be used to implement a prof essional-quality tv encoder with the digital processing part implemented in the cyclone iv e fpga. figure 4-30 shows a block diagram of a tv encoder implemented in this manner. figure 4-30 a tv encoder that uses the cyclone iv e fpga and the adv7123 61 4 4 . . 1 1 7 7 u u s s i i n n g g t t h h e e u u s s b b i i n n t t e e r r f f a a c c e e the de2-115 board provides both usb host a nd device interfaces using the philips isp1362 single-chip usb controller. the hos t and device controllers are compliant with the universal serial bus specification rev. 2.0, supporting data transfer at full-speed (12 mbit/s) and low-speed (1.5 mbit/s). figure 4-31 sh ows the schematic diagram of the usb circuitry; the pin assignments for the associated interface are listed in table 4-25 . detailed inform ation for using the isp1362 device is available in its datasheet and programming guide; both documents can be found on th e manufacturer?s website, or in the de2_115_datasheets\usb folder on the de2-115 system cd. the most challenging part of a usb application is in the design of the software driver needed. two complete examples of usb drivers, for both host and device applications, can be found in sections 6.4 and 6.5. these demonstrations provide examples of software dr ivers for the nios ii processor. figure 4-31 connections between fpga and usb (isp1362) table 4-25 usb (isp1362) pin assignments signal name fpga pin no. description i/o standard otg_addr[0] pin_h7 isp1362 address[0] 3.3v otg_addr[1] pin_c3 isp1362 address[1] 3.3v otg_data[0] pin_j6 isp1362 data[0] 3.3v otg_data[1] pin_k4 isp1362 data[1] 3.3v otg_data[2] pin_j5 isp1362 data[2] 3.3v otg_data[3] pin_k3 isp1362 data[3] 3.3v otg_data[4] pin_j4 isp1362 data[4] 3.3v otg_data[5] pin_j3 isp1362 data[5] 3.3v otg_data[6] pin_j7 isp1362 data[6] 3.3v otg_data[7] pin_h6 isp1362 data[7] 3.3v 62 otg_data[8] pin_h3 isp1362 data[8] 3.3v otg_data[9] pin_h4 isp1362 data[9] 3.3v otg_data[10] pin_g1 isp1362 data[10] 3.3v otg_data[11] pin_g2 isp1362 data[11] 3.3v otg_data[12] pin_g3 isp1362 data[12] 3.3v otg_data[13] pin_f1 isp1362 data[13] 3.3v otg_data[14] pin_f3 isp1362 data[14] 3.3v otg_data[15] pin_g4 isp1362 data[15] 3.3v otg_cs_n pin_a3 isp1362 chip select 3.3v otg_rd_n pin_b3 isp1362 read 3.3v otg_wr_n pin_a4 isp1362 write 3.3v otg_rst_n pin_c5 isp1362 reset 3.3v otg_int[0] pin_a6 isp1362 interrupt 0 3.3v otg_int[1] pin_d5 isp1362 interrupt 1 3.3v otg_dack_n[0] pin_c4 isp1362 dma acknowledge 0 3.3v otg_dack_n[1] pin_d4 isp1362 dma acknowledge 1 3.3v otg_dreq[0] pin_j1 isp1362 dma request 0 3.3v otg_dreq[1] pin_b4 isp1362 dma request 1 3.3v otg_fspeed pin_c6 usb full speed, 0 = enable, z = disable 3.3v otg_lspeed pin_b6 usb low speed, 0 = enable, z = disable 3.3v 4 4 . . 1 1 8 8 u u s s i i n n g g i i r r the de2-115 provides an infrared remote-c ontrol receiver module (m odel: irm-v538n7/tr1), whose datasheet is offered in the de2_115_datasheets\ir_receiver folder on de2-115 system cd. note that for this all-in-one re ceiver module, it is only compatible with the 38khz carrier standard, with a maximum data rate of about 4kbps for its product information. the accompanied remote controller with an encoding chip of upd6121g is very suita ble of generating expected infrared signals. figure 4-32 shows the related schem atic of the ir receiver, and the pin assignments of the associated interface are listed in table 4-26 . figure 4-32 connection between fpga and ir 63 table 4-26 ir pin assignments signal name fpga pin no. description i/o standard irda_rxd pin_y15 ir receiver 3.3v 4 4 . . 1 1 9 9 u u s s i i n n g g s s r r a a m m / / s s d d r r a a m m / / f f l l a a s s h h / / e e e e p p r r o o m m / / s s d d c c a a r r d d ? sram the de2-115 board has 2mb sram memory with 16-bit data width. be ing featured with a maximum performance frequency of about 125mh z under the condition of standard 3.3v single power supply makes it suitable of dealing with high- speed media processing applications that need ultra data throughput. the related schematic is shown in figure 4-33 . figure 4-33 connections between fpga and sram ? sdram the board features 128mb of sdram, implem ented using two 64mb sdram devices. each device consists of separate 16-bit data lines conn ected to the fpga, and sh ared control and address lines. these chips use the 3.3v lvcmos signa ling standard. connections between fpga and sdram are shown in figure 4-34 . 64 figure 4-34 connections between fpga and sdram ? flash the board is assembled with 8mb of flash memory using an 8-bit data bus. the device uses 3.3v cmos signaling standard. because of its non-vola tile property, it is usua lly used for storing software binaries, images, sounds or other media. connections between fpga and flash are shown in figure 4-35 . figure 4-35 connections between fpga and flash 65 ? eeprom the board has 32kb eeprom. with the benefit of i2 c bus, users could use it as residence of user data like version information, mac addr ess or other description substance. figure 4-36 gives the schematic view of the eeprom. the configured access address of eeprom is 0xa0 for writing and 0xa1 for reading. figure 4-36 connections between fpga and eeprom ? sd card many applications use a large external storage device, such as sd card or cf card, for storing data. the de2-115 board provides the hardware needed for sd card access. users can implement custom controllers to access the sd card in spi mode and sd card 4-bit or 1-bit mode. figure 4-37 shows the related signals. finally , table 4-27~ table 4-30 lis ts all the associated pins for interfacing fpga respectively. 66 figure 4-37 connections between fpga and sd card socket table 4-27 sram pin assignments signal name fpga pin no. description i/o standard sram_addr[0] pin_ab7 sram address[0] 3.3v sram_addr[1] pin_ad7 sram address[1] 3.3v sram_addr[2] pin_ae7 sram address[2] 3.3v sram_addr[3] pin_ac7 sram address[3] 3.3v sram_addr[4] pin_ab6 sram address[4] 3.3v sram_addr[5] pin_ae6 sram address[5] 3.3v sram_addr[6] pin_ab5 sram address[6] 3.3v sram_addr[7] pin_ac5 sram address[7] 3.3v sram_addr[8] pin_af5 sram address[8] 3.3v sram_addr[9] pin_t7 sram address[9] 3.3v sram_addr[10] pin_af2 sram address[10] 3.3v sram_addr[11] pin_ad3 sram address[11] 3.3v sram_addr[12] pin_ab4 sram address[12] 3.3v sram_addr[13] pin_ac3 sram address[13] 3.3v sram_addr[14] pin_aa4 sram address[14] 3.3v sram_addr[15] pin_ab11 sram address[15] 3.3v sram_addr[16] pin_ac11 sram address[16] 3.3v sram_addr[17] pin_ab9 sram address[17] 3.3v sram_addr[18] pin_ab8 sram address[18] 3.3v sram_addr[19] pin_t8 sram address[19] 3.3v sram_dq[0] pin_ah3 sram data[0] 3.3v sram_dq[1] pin_af4 sram data[1] 3.3v sram_dq[2] pin_ag4 sram data[2] 3.3v sram_dq[3] pin_ah4 sram data[3] 3.3v sram_dq[4] pin_af6 sram data[4] 3.3v sram_dq[5] pin_ag6 sram data[5] 3.3v sram_dq[6] pin_ah6 sram data[6] 3.3v 67 sram_dq[7] pin_af7 sram data[7] 3.3v sram_dq[8] pin_ad1 sram data[8] 3.3v sram_dq[9] pin_ad2 sram data[9] 3.3v sram_dq[10] pin_ae2 sram data[10] 3.3v sram_dq[11] pin_ae1 sram data[11] 3.3v sram_dq[12] pin_ae3 sram data[12] 3.3v sram_dq[13] pin_ae4 sram data[13] 3.3v sram_dq[14] pin_af3 sram data[14] 3.3v sram_dq[15] pin_ag3 s ram data[15] 3.3v sram_oe_n pin_ad5 sram output enable 3.3v sram_we_n pin_ae8 sram write enable 3.3v sram_ce_n pin_af8 sram chip select 3.3v sram_lb_n pin_ad4 sram lower byte strobe 3.3v sram_ub_n pin_ac4 sram higher byte strobe 3.3v table 4-28 sdram pin assignments signal name fpga pin no. description i/o standard dram_addr[0] pin_r6 sdram address[0] 3.3v dram_addr[1] pin_v8 sdram address[1] 3.3v dram_addr[2] pin_u8 sdram address[2] 3.3v dram_addr[3] pin_p1 sdram address[3] 3.3v dram_addr[4] pin_v5 sdram address[4] 3.3v dram_addr[5] pin_w8 sdram address[5] 3.3v dram_addr[6] pin_w7 sdram address[6] 3.3v dram_addr[7] pin_aa7 sdram address[7] 3.3v dram_addr[8] pin_y5 sdram address[8] 3.3v dram_addr[9] pin_y6 sdram address[9] 3.3v dram_addr[10] pin_r5 sdram address[10] 3.3v dram_addr[11] pin_aa5 sdram address[11] 3.3v dram_addr[12] pin_y7 sdram address[12] 3.3v dram_dq[0] pin_w3 sdram data[0] 3.3v dram_dq[1] pin_w2 sdram data[1] 3.3v dram_dq[2] pin_v4 sdram data[2] 3.3v dram_dq[3] pin_w1 sdram data[3] 3.3v dram_dq[4] pin_v3 sdram data[4] 3.3v dram_dq[5] pin_v2 sdram data[5] 3.3v dram_dq[6] pin_v1 sdram data[6] 3.3v dram_dq[7] pin_u3 sdram data[7] 3.3v dram_dq[8] pin_y3 sdram data[8] 3.3v dram_dq[9] pin_y4 sdram data[9] 3.3v dram_dq[10] pin_ab1 sdram data[10] 3.3v dram_dq[11] pin_aa3 sdram data[11] 3.3v dram_dq[12] pin_ab2 sdram data[12] 3.3v dram_dq[13] pin_ac1 sdram data[13] 3.3v dram_dq[14] pin_ab3 sdram data[14] 3.3v dram_dq[15] pin_ac2 sdram data[15] 3.3v 68 dram_dq[16] pin_m8 sdram data[16] 3.3v dram_dq[17] pin_l8 sdram data[17] 3.3v dram_dq[18] pin_p2 sdram data[18] 3.3v dram_dq[19] pin_n3 sdram data[19] 3.3v dram_dq[20] pin_n4 sdram data[20] 3.3v dram_dq[21] pin_m4 sdram data[21] 3.3v dram_dq[22] pin_m7 sdram data[22] 3.3v dram_dq[23] pin_l7 sdram data[23] 3.3v dram_dq[24] pin_u5 sdram data[24] 3.3v dram_dq[25] pin_r7 sdram data[25] 3.3v dram_dq[26] pin_r1 sdram data[26] 3.3v dram_dq[27] pin_r2 sdram data[27] 3.3v dram_dq[28] pin_r3 sdram data[28] 3.3v dram_dq[29] pin_t3 sdram data[29] 3.3v dram_dq[30] pin_u4 sdram data[30] 3.3v dram_dq[31] pin_u1 sdram data[31] 3.3v dram_ba[0] pin_u7 sdram bank address[0] 3.3v dram_ba[1] pin_r4 sdram bank address[1] 3.3v dram_dqm[0] pin_u2 sdram byte data mask[0] 3.3v dram_dqm[1] pin_w4 sdram byte data mask[1] 3.3v dram_dqm[2] pin_k8 sdram byte data mask[2] 3.3v dram_dqm[3] pin_n8 sdram byte data mask[3] 3.3v dram_ras_n pin_u6 sdram row address strobe 3.3v dram_cas_n pin_v7 sdram column address strobe 3.3v dram_cke pin_aa6 sdram clock enable 3.3v dram_clk pin_ae5 sdram clock 3.3v dram_we_n pin_v6 sdram write enable 3.3v dram_cs_n pin_t4 sdram chip select 3.3v table 4-29 flash pin assignments signal name fpga pin no. description i/o standard fl_addr[0] pin_ag12 flash address[0] 3.3v fl_addr[1] pin_ah7 flash address[1] 3.3v fl_addr[2] pin_y13 flash address[2] 3.3v fl_addr[3] pin_y14 flash address[3] 3.3v fl_addr[4] pin_y12 flash address[4] 3.3v fl_addr[5] pin_aa13 flash address[5] 3.3v fl_addr[6] pin_aa12 flash address[6] 3.3v fl_addr[7] pin_ab13 flash address[7] 3.3v fl_addr[8] pin_ab12 flash address[8] 3.3v fl_addr[9] pin_ab10 flash address[9] 3.3v fl_addr[10] pin_ae9 flash address[10] 3.3v fl_addr[11] pin_af9 flash address[11] 3.3v fl_addr[12] pin_aa10 flash address[12] 3.3v fl_addr[13] pin_ad8 flash address[13] 3.3v fl_addr[14] pin_ac8 flash address[14] 3.3v 69 fl_addr[15] pin_y10 flash address[15] 3.3v fl_addr[16] pin_aa8 flash address[16] 3.3v fl_addr[17] pin_ah12 flash address[17] 3.3v fl_addr[18] pin_ac12 flash address[18] 3.3v fl_addr[19] pin_ad12 flash address[19] 3.3v fl_addr[20] pin_ae10 flash address[20] 3.3v fl_addr[21] pin_ad10 flash address[21] 3.3v fl_addr[22] pin_ad11 flash address[22] 3.3v fl_dq[0] pin_ah8 flash data[0] 3.3v fl_dq[1] pin_af10 flash data[1] 3.3v fl_dq[2] pin_ag10 flash data[2] 3.3v fl_dq[3] pin_ah10 flash data[3] 3.3v fl_dq[4] pin_af11 flash data[4] 3.3v fl_dq[5] pin_ag11 flash data[5] 3.3v fl_dq[6] pin_ah11 flash data[6] 3.3v fl_dq[7] pin_af12 flash data[7] 3.3v fl_ce_n pin_ag7 flash chip enable 3.3v fl_oe_n pin_ag8 flash output enable 3.3v fl_rst_n pin_ae11 flash reset 3.3v fl_ry pin_y1 flash ready/busy output 3.3v fl_we_n pin_ac10 flash write enable 3.3v fl_wp_n pin_ae12 flash write prot ect /programming acceleration 3.3v table 4-30 eeprom pin assignments signal name fpga pin no. description i/o standard eep_i2c_sclk pin_d14 eeprom clock 3.3v eep_i2c_sdat pin_e14 eeprom data 3.3v table 4-31 sd card socket pin assignments signal name fpga pin no. description i/o standard sd_clk pin_ae13 sd clock 3.3v sd_cmd pin_ad14 sd command line 3.3v sd_dat[0] pin_ae14 sd data[0] 3.3v sd_dat[1] pin_af13 sd data[1] 3.3v sd_dat[2] pin_ab14 sd data[2] 3.3v sd_dat[3] pin_ac14 sd data[3] 3.3v sd_wp_n pin_af14 sd write protect 3.3v 70 chapter 5 de2-115 system builder this chapter describes how users can create a cu stom design project on the de2-115 board by using de2-115 software tool ? de2-115 system builder. 5 5 . . 1 1 i i n n t t r r o o d d u u c c t t i i o o n n the de2-115 system builder is a windows based soft ware utility, designed to assist users to create a quartus ii project for the de2-115 board within minutes. the generated quartus ii project files include: ? quartus ii project file (.qpf) ? quartus ii setting file (.qsf) ? top-level design file (.v) ? synopsis design constraints file (.sdc) ? pin assignment document (.htm) by providing the above files, de2-115 system build er prevents occurrence of situations that are prone to errors when users manually edit the t op-level design file or place pin assignments. the common mistakes that users encounter are the following: 1. board damaged for wrong pin/ bank voltage assignments. 2. board malfunction caused by wrong device conn ections or missing pin counts for connected ends. 3. performance degeneration because of improper pin assignments. 5 5 . . 2 2 g g e e n n e e r r a a l l d d e e s s i i g g n n f f l l o o w w this section will introduce the general design flow to build a project for th e de2-115 board via the de2-115 system builder. the general design flow is illustrated in figure 5-1 . users should launch d e2-115 system builder and create a new project acco rding to their design requirements. when users complete the settings , the de2-115 system builder will generate two major files which include top-level design file (.v) and quartus ii se tting file (.qsf). 71 the top-level design file contains top-level ve rilog hdl wrapper for users to add their own design/logic. the quartus ii setting file contains information such as fpga device type, top-level pin assignment, and i/o standard for each user-defined i/o pin. finally, quartus ii programmer must be used to download sof file to de2-115 board using jtag interface. start launch quartus ii and open project add user design/logic compile to generate .sof configure fpga end .qpf .qsf .v .htm .sdc launch de2-115 system builder create new de2-115 system builder project generate quartus ii project and document figure 5-1 the general design flow of building a design 5 5 . . 3 3 u u s s i i n n g g d d e e 2 2 - - 1 1 1 1 5 5 s s y y s s t t e e m m b b u u i i l l d d e e r r this section provides the detail ed procedures on how the de2-115 system builder is used. ? install and launch the de2-115 system builder the de2-115 system builder is located in the directory: "de2_115_tools\de2_115_system_builder" on the de2-115 system cd. users can copy the whole folder to a host computer without installing the utility. launch the de2-115 system builder by executing the de2_115_systembuilder.exe on the hos t computer and the gui window will appear as shown in figure 5-2 . 72 figure 5-2 the de2-115 system builder window ? input project name input project name as show in figure 5-3 . project name: t ype in an appropriate name here, it will automatically be assigned as the name of your top-level design entity. figure 5-3 the de2-115 board type and project name 73 ? system configuration under system configuration users are given the flexibility of enabling their choice of included components on the de2-115 as shown in figure 5-4 . each com ponent of the de2-115 is listed where users can enable or disable a component acco rding to their design by simply marking a check or removing the check in the field provided. if the component is enabled, the de2-115 system builder will automatically generate the associat ed pin assignments including the pin name, pin location, pin direction, and i/o standard. figure 5-4 system configuration group ? gpio expansion users can connect gpio expansion card onto gpio header located on the de2-115 board as shown in figure 5-5 . select the appropriate daught er card you wish to includ e in your design from the drop-down menu. the system builder will automatical ly generate the associated pin assignments including the pin name, pin location, pin direction, and io standard. if a customized daughter board is used, users ca n select ?gpio default? followed by changing the pin name, pin direction, and io standard according to the specification of the customized daughter board. 74 figure 5-5 gpio expansion group the ?prefix name? is an optional feature which de notes the prefix pin name of the daughter card assigned in your design. users ma y leave this field empty. ? hsmc expansion users can connect hsmc-interfaced daughter car ds onto hsmc located on the de2-115 board shown in figure 5-6 . select the daughter card you wish to add to your design under the appropriate hsmc connector where the daughter card is connect ed to. t he system builder will automatically generate the associated pin a ssignment including pin name, pin location, pin direction, and io standard. 75 figure 5-6 hsmc expansion group the ?prefix name? is an optional feature that denotes the pin name of the daughter card assigned in your design. users may leave this field empty. ? project setting management the de2-115 system builder also provides functions to restore default setting, loading a setting, and saving users? board c onfiguration file shown in figure 5-7 . users can save the current board configuration information into a .cfg file and load it to the de2-115 system builder. figure 5-7 project settings 76 ? project generation when users press the generate button, the de2-115 system builder will generate the corresponding quartus ii files and documents as listed in the table 5-1 : t able 5-1 the files generated by de2-115 system builder no. filename description 1 77 chapter 6 examples of advanced demonstrations this chapter provides a number of examples of advanced circuits implemented on the de2-115 board. these circuits provide dem onstrations of the major features on the board, such as its audio and video capabilities, usb, a nd ethernet connectivity. for each demonstration the cyclone iv e fpga (or epcs64 serial eeprom) conf iguration file is provided, as well as the full source code in verilog hdl. all of the associated files can be found in the de2_115_demonstrations folder on the de2-115 system cd. for each demonstrations descri bed in the following sections, the name of the project directory for its files is gi ven, which are subdirectories of the de2_115_demonstrations folder. ? installing the demonstrations to install the demonstrations on your computer: copy the directory de2_115_demonstrations into a local directory of your choice. it is important to ensure that the path to your loca l directory contains no spaces ? othe rwise, the nios ii software will not work. note quartus ii v9.1 sp2 is requ ired for all de2-115 demonstrations to support cyclone iv e device. quartus ii v10.0 ca n be installed from the alte ra complete design suite dvd provided. 6 6 . . 1 1 d d e e 2 2 - - 1 1 1 1 5 5 f f a a c c t t o o r r y y c c o o n n f f i i g g u u r r a a t t i i o o n n the de2-115 board is shipped from the factory with a default configuration bit-stream that demonstrates some of the basic features of the board. the setup required fo r this demonstration, and the locations of its files are shown below. ? demonstration setup, file lo cations, and instructions ? project directory: de2_115_default ? bit stream used: de2_115_defau lt.sof or de2_115_default.pof ? power on the de2-115 board, with the usb cable connected to the usb blaster port. if necessary (that is, if the defa ult factory configuration of the de2-115 board is not currently 78 stored in epcs64 device), downl oad the bit stream to the board by using either jtag or as programming ? you should now be able to obser ve that the 7-segment displays are displaying a sequence of characters, and the red and green leds are flas hing. also, ?welcome to the altera de2-115? is shown on the lcd display ? optionally connect a vga display to the vga d-sub connector. when connected, the vga display should show a color picture ? optionally connect a powered speaker to the stereo audio-out jack ? place slide switch sw17 in the down position to hear a 1 khz humming sound from the audio-out port. alternatively, if slide switc h sw17 is in the up position, and optionally connects the microphone in port with a microphone and/or connects the line-in port with an audio player's output, you will hear the sound fr om the microphone or audio player or mixed sound from both. the verilog hdl source code for this demonstration is provided in the de2_115_default folder , which also includes the necessary files for the corresponding quartus ii project. the top-level verilog hdl file, called de2_115_default.v, can be us ed as a template for other projects, because it defines ports that correspond to all of the us er-accessible pins on the cyclone iv e fpga. 6 6 . . 2 2 t t v v b b o o x x d d e e m m o o n n s s t t r r a a t t i i o o n n this demonstration plays video and audio input from a dvd player using the vga output, audio codec, and one tv decoder (u6) on the de2-115 board. figure 6-1 shows the block diagram of the design. there are tw o major blocks in the ci rcuit, called i2c_av_c onfig and tv_to_vga. the tv_to_vga block consists of the itu-r 656 decoder, sdram frame buffer, yuv422 to yuv444, ycrcb to rgb, and vga controller. the figure also shows the tv decoder (adv7180) and the vga dac (adv7123) chips used. as soon as the bit stream is downloaded into the fpg a, the register values of the tv decoder chip are used to configure th e tv decoder via the i2c_av_config bl ock, which uses the i2c protocol to communicate with the tv decoder chip. followi ng the power-on sequence, the tv decoder chip will be unstable for a time period; the lock detector is responsible for detecting this instability. the itu-r 656 decoder block extrac ts ycrcb 4:2:2 (yuv 4:2:2) video signals from the itu-r 656 data stream sent from the tv decoder. it also generates a data valid co ntrol signal indicating the valid period of data output. because the video signal from the tv dec oder is interlaced, we need to perform de-interlacing on the data source. we us ed the sdram frame buffer and a field selection multiplexer (mux) which is controlled by the vg a controller to perform the de-interlacing operation. internally, the vga contro ller generates data request and odd/even selection signals to the sdram frame buffer and filed selecti on multiplexer (mux). th e yuv422 to yuv444 block converts the selected ycrcb 4:2:2 (yuv 4:2:2) video data to the ycrcb 4:4:4 (yuv 4:4:4) video data format. 79 finally, the ycrcb_to_rgb block converts the ycrcb data into rgb data output. the vga controller block generates standard vga sync hronous signals vga_hs and vga_vs to enable the display on a vga monitor. figure 6-1 block diagram of the tv box demonstration ? demonstration setup, file lo cations, and instructions ? project directory: de2_115_tv ? bit stream used: de2_115_tv.sof or de2_115_tv.pof ? connect a dvd player?s composite video output (y ellow plug) to the video-in rca jack (j12) of the de2-115 board. the dvd player ha s to be configured to provide: o ntsc output o 60hz refresh rate o 4:3 aspect ratio o non-progressive video ? connect the vga output of the de2-115 board to a vga monitor (both lcd and crt type of monitors should work) ? connect the audio output of th e dvd player to the line-in port of the de2-115 board and connect a speaker to the line-out port. if the audio output jacks from the dvd player are rca type, then an adaptor will be needed to c onvert to the mini-stere o plug supported on the de2-115 board; this is the same type of plug supported on most computers ? load the bit stream into fpga by execu te the batch file ?de2_115_tv.bat? under de2_115_tv\demo_batch\ folder ? press key0 on the de2-115 board to reset the circuit 80 note: if the hsmc loopback adapter is mounted, the i2c_scl will be directly routed back to i2c_sda. because audio chip, tv decoder chip and hsmc share one i2c bus, therefore audio and video chip won?t function correctly. figure 6-2 illustrates the setup for this dem onstration. figure 6-2 the setup for the tv box demonstration 6 6 . . 3 3 u u s s b b p p a a i i n n t t b b r r u u s s h h usb port is widely used in many multimedia products. the de2-115 board provides a complete usb solution for both host and device applicati ons. in this demonstration, we implement a paintbrush application by using a usb mouse as the input device. this demonstration uses the device port of the ph ilips isp1362 chip and the nios ii processor to implement a usb mouse movement detector. we al so implemented a video frame buffer with a vga controller to perform the real -time image storage and display. figure 6-3 shows the block diagram of the circuit, which allows the user to draw lines on the vga di splay screen using the usb mouse. the vga controller bloc k is integrated into the altera avalon bus so that it can be controlled by the nios ii processor. once the program runs, the nios ii processor is started as it will detect the existence of the usb 81 mouse connected to de2-115 board. when the mouse moves, the nios ii processor is able to keep track of the movement and record it in a frame bu ffer memory. the vga cont roller will overlap the data stored in the frame buffer with a default im age pattern and display the overlapped image on the vga display. figure 6-3 block diagram of the usb paintbrush demonstration ? demonstration setup, file lo cations, and instructions project directory: de2_115_nios_host_mouse_vga bit stream used: de2_115_n ios_host_mouse_vga.sof nios ii workspace: de2_115_nios_host_mouse_vga\software ? connect a usb mouse to the usb host connector (type a) of the de2-115 board ? connect the vga output of the de2-115 board to a vga monitor (both lcd and crt type of monitors should work) ? load the bit stream into fpga(note*) ? run the nios ii and choose de2_115_nios_host _mouse_vga\software as the workspace. click on the run button(note*) ? you should now be able to obser ve a blue background with an altera logo on the vga display ? move the usb mouse and observe the correspo nding movements of the cursor on the screen ? left-click mouse to draw white dots/lines and ri ght-click the mouse to draw blue dots/lines on the screen. note: execute de2_115_nios_host_mouse_vga\demo_bat ch\nios_host_mouse_vga.bat will download .sof and .elf files. 82 figure 6-4 illustrates the setup for this demonstration. figure 6-4 the setup for the usb paintbrush demonstration 6 6 . . 4 4 u u s s b b d d e e v v i i c c e e most usb applications and products operate as usb devices, rather than usb hosts. in this demonstration, we show how the de2-115 board can operate as a usb device that can be connected to a host computer. as indicated in the block diagram in figure 6-5 , the nios ii processor is used to communicate with the h ost computer via host port on the de2-115 board?s philips isp1362 device. after connecting the de2-115 board to a usb port on the host comput er, a software program has to be executed on the nios ii processor to initiali ze the philips isp1362 chip. once the software program is successfully executed, the host computer will identify the new device in its usb device list and asks for the associated driver; the de vice will be identified as a philips pdiusbd12 smart evaluation board. after comple tion of the driver installation on the host com puter, the next step is to run a software program on the hos t computer called isp1362dcusb.exe; this program communicates with the de2-115 board. in the isp1362dcusb program, c licking on the add button in the window panel of the software causes the host computer to send a particular usb packet to the de2-115 board; the packet will be received by the nios ii processor and will incremen t the value of a hardware counter. the value of the counter is displayed on one of the board?s 7- segment displays, and also on the green leds. if the user clicks on the clear butt on in the window panel of the soft ware driver, the host computer 83 sends a different usb packet to the board, which cau ses the nios ii processo r to clear the hardware counter to zero. figure 6-5 block diagram of the usb device demonstration ? demonstration setup, file lo cations, and instructions ? project directory: de2_115_nios_device_led ? bit stream used: de2_115_n ios_device_led.sof ? nios ii workspace: de2_115_nios_device_led\software ? borland c++ software driver : de2_115_nios_device_led\sw ? connect the usb device connector of the de2- 115 board to the host computer using a usb cable (type ab). ? load the bit stream into fpga(note*) ? run nios ii ide with de2_115_nios_device_ led\software as the workspace. click on run(note*) ? a new usb hardware device will be detected. specify the location of the driver as de2_115_nios_device_led\d12test.inf (philips pdiusbd12 smart evaluation board). ignore any warning messages pr oduced during installation ? the host computer should repor t that a philips pdiusbd12 smart evaluation board is now installed ? execute the software: de2_115_nios_device _led\sw\isp1362dcusb.exe on the host computer. then, experiment with the softwa re by clicking on the add and clear buttons 84 note: execute de2_115_nios_device_led \demo_batch\nios_device_led.bat will download .sof and .elf files. figure 6-6 illustrates the setup for this dem onstration. figure 6-6 setup for the usb device demonstration 6 6 . . 5 5 a a k k a a r r a a o o k k e e m m a a c c h h i i n n e e this demonstration uses the mi crophone-in, line-in, and line-out ports on the de2-115 board to create a karaoke machine application. the wolf son wm8731 audio codec is configured in the master mode, with which the audio codec gene rates ad/da serial bit clock (bck) and the left/right channel clock (lrck) automatically. as indicated in figure 6-7 , the i2c interface is used to configure the audio codec. the sample rate and gain of the c odec are set in this manner, and the data input from the line-in por t is then mixed with the microphone -in port and the result is sent to the line-out port. for this demonstration the sample rate is set to 48khz. pressing the pushbutton key0 reconfigures the gain of the audio codec via i2c bus, cycling w ithin ten predefined gain values (volume levels) provided by the device. 85 figure 6-7 block diagram of the karaoke machine demonstration ? demonstration setup, file lo cations, and instructions ? project directory: de2_115_i2sound ? bit stream used: de2_115_i2s ound.sof or de2_115_i2sound.pof ? connect a microphone to the microphone-in port (pink color) on the de2-115 board ? connect the audio output of a musi c-player, such as an mp3 player or computer, to the line-in port (blue color) on the de2-115 board ? connect a headset/speaker to the line-out port (green color) on the de2-115 board ? load the bit stream into the fpga by ex ecute the batch file ?de2_115_i2sound? under the de2_115_i2sound\demo_batch folder ? you should be able to hear a mixture of th e microphone sound and the sound from the music player ? press key0 to adjust the volume; it cycles between volume levels 0 to 9 note: if the hsmc loopback adapter is mounted, the i2c_scl will be directly routed back to i2c_sda. because audio chip, tv decoder chip and hsmc share one i2c bus, therefore audio and video chip won?t function correctly. figure 6-8 illustrates the setup for this dem onstration. 86 figure 6-8 the setup for the karaoke machine 6 6 . . 6 6 s s d d c c a a r r d d d d e e m m o o n n s s t t r r a a t t i i o o n n many applications use a large external storage device, such as an sd card or cf card to store data. the de2-115 board provides the hardware and so ftware needed for sd card access. in this demonstration we will show how to browse files stor ed in the root directory of an sd card and how to read the file contents of a specific file. the sd card is required to be formatted as fat file system in advance. long file name is supported in this demonstration. figure 6-9 shows the hardware system block diagram of this demonstration. the system requires a 50mhz clock provided by the board. the pll generates a 100mhz cl ock for the nios ii processor and other controllers. four pio pins are connected to the sd card socket. sd 4-bit mode is used to access the sd card hardware. the sd 4-bit prot ocol and fat file system function are all implemented by nios ii software. the softwa re is stored in the on-chip memory. 87 figure 6-9 block diagram of the sd card demonstration figure 6-10 shows the software stack of this demonstr ation. the nios pio bl ock provides basic io functions to access hardware directly. the functi ons are provided from nios ii system and the function prototype is defined in the header file 88 main fat file system sd card nios ii pio figure 6-10 software stack of the sd card demonstration d d e e m m o o n n s s t t r r a a t t i i o o n n s s o o u u r r c c e e c c o o d d e e ? project directory: de2_115_sd_card ? bit stream used: de2_115_sd_card.sof ? nios ii workspace: de2_115_sd_card\software d d e e m m o o n n s s t t r r a a t t i i o o n n b b a a t t c c h h f f i i l l e e demo batch file folder: de2_115_sd_card \demo_batch the demo batch file includes the following files: ? batch file: de2_115_sd_card.ba t, de2_115_sd_card_bashrc ? fpga configure file: de2_115_sd_card.sof ? nios ii program: de2_115_sd_card.elf d d e e m m o o n n s s t t r r a a t t i i o o n n s s e e t t u u p p ? make sure quartus ii and nios ii are installed on your pc. ? power on the de2-115 board. ? connect usb blaster to the de2-115 board and install usb blaster dr iver if necessary. ? execute the demo batch file ?de2_115_sd_ card.bat? under the batch file folder, de2_115_sd_card\demo_batch. ? after nios ii program is downloaded and executed successfully, a prompt message will be displayed in nios2-terminal. ? copy test files to the root directory of the sd card. ? insert the sd card into the sd ca rd socket of de2-115, as shown in figure 6-11 . ? press key3 of the de2-115 board to start reading sd card. ? the program will display sd card inform ation, as shown in figure 6-12 . 89 figure 6-11 insert sd card for the sd card demonstration figure 6-12 running results of the sd card demonstration 6 6 . . 7 7 s s d d c c a a r r d d m m u u s s i i c c p p l l a a y y e e r r many commercial media/audio players use a large exte rnal storage device, such as an sd card or cf card, to store music or video f iles. such players may also incl ude high-quality dac devices so that good audio quality can be produced. the de2- 115 board provides the hardware and software needed for sd card access and pr ofessional audio performance so that it is possible to design advanced multimedia products using the de2-115 board. in this demonstration we show how to implemen t an sd card music player on the de2-115 board, in which the music files are stored in an sd ca rd and the board can play the music files via its cd-quality audio dac circuits. we use the nios ii processor to read the music data stored in the sd card and use the wolfson wm8731 audio codec to play the music. 90 figure 6-13 shows the hardware block diagram of this demonstration. the system requires a 50 mhz clock provided from the boar d. the pll generates a 100mhz clock for nios ii processor and the other controllers except for the audio controll er. the audio chip is controlled by the audio controller which is a user-defin ed sopc component. this audio c ontroller needs an input clock of 18.432 mhz. in this design, the cloc k is provided by the pll block. the audio controller requires the audio chip working in master mode, so the se rial bit (bck) and the left/right channel clock (lrck) are provided by the audio chip. the 7- segment display is controlled by the seg7 controller which also is a user-defined sopc component. two pio pins are connected to the i2c bus. the i2c protocol is implemented by software. four pio pins are conn ected to the sd card socket. the ir receiver is controlled by the ir controller which also is a user-defined sopc component. sd 4-bit mode is used to access the sd card and is implemented by software. all of the other sopc components in the block diag ram are sopc builder built-in components. figure 6-13 block diagram of the sd music player demonstration figure 6-14 shows the software stack of this demonstr ation. sd 4-bit mode block implements the sd 4-bit mode protocol for reading raw data from the sd card. the fat block implements fat16/fat32 file system for readi ng wave files that is stored in the sd card. in this block, only read function is implemented. the wave lib bloc k implements wave file decoding function for extracting audio data from wave files. the i2c block implements i2c protocol for configuring audio chip. the seg7 block implements displayi ng function to display el apsed playing time. the audio block implements audio fifo checking func tion and audio signal sendi ng/receiving function. the ir block acts as a control interface of the music player system. 91 main nios hal system call seg7 i2c audio wave lib fat16/fat32 sd 4-bit mode ir receiver figure 6-14 software stack of the sd music player demonstration the audio chip should be configured before se nding audio signal to the audio chip. the main program uses i2c protocol to c onfigure the audio chip working in master mode; the audio output interface working in i2s 16-bits per channel and with sampling ra te according to the wave file contents. in audio playing loop, the main program reads 512-byte audi o data from the sd card, and then writes the data to dac fifo in the audio c ontroller. before writing th e data to the fifo, the program will verify if the fifo is full. the design also mixes the audio signal from the microphone-in and line-in for the karaoke-style effects by enabling the bypass and sitetone functions in the audio chip. finally, users can obtain the st atus of the sd music player from the 16x2 lcd module, the 7-segment display, and the leds. the top and botto m row of the lcd module will display the file name of the music that is played on the de2-115 board and the value of music volume, respectively. the 7-segment displays will show the elapsed time of the playing music file. the led will indicate the audio signal strength. ? demonstration setup, file lo cations, and instructions ? project directory: de 2_115_sd_card_audio_player ? bit stream used: de2_115_sd_card_audio_player.sof ? nios ii workspace: de2_115_sd_card_audio_player\software ? format your sd card into fat16/fat32 format ? place the wave files to the root directory of th e sd card. the provided wave files must have a sample rate of either 96k, 48k, 44.1k, 32k, or 8k. in addition, the wave files must be stereo and 16 bits per channel. ? load the bitstream into the fpga on the de2-115 board(note*1) ? run the nios ii software under the workspace de2_115_sd_card_audio_player\software(note*1) 92 ? connect a headset or speaker to the de2-115 board and you should be able to hear the music played from the sd card ? press key3 on the de2-115 board to play the next music file stored in the sd card. ? press key2 and key1 to increase and decr ease the output music volume respectively. ? users can also use the remote control to play/pause the music, select the last/next music file to play and control volume. the detailed information about each function of remote controller is shown in table 6-1 . table 6-1 detailed information of th e button on the remote controller button name function description play play music or pause music channel select last/next music file to play volume turn up/down volume mute mute/un-mute note: 1. execute the batch file de2_1 15_sd_card_audio_player\demo_batch \ de2_115_sd_card_audio_player.bat to download both hardware and software bit stream 2. if the capacity of your sd memory card is more than or equal 8gb, pl ease make sure it has the performance more than or equal to class 4 3. if the hsmc loopback adapter is mounted, the i2c_scl will be directly routed back to i2c_sda. because audio chip, tv decoder chip and hsmc share one i2c bus, therefore audio and video chip won?t function correctly. figure 6-15 illus trates the setup for this demonstration. 93 figure 6-15 the setup for the sd music player demonstration 6 6 . . 8 8 p p s s / / 2 2 m m o o u u s s e e d d e e m m o o n n s s t t r r a a t t i i o o n n we offer this simple ps/2 controller coded in verilog hdl to dem onstrate bidirectional communication between ps/2 controller and the devi ce, the ps/2 mouse. you can treat it as a how-to basis and develop your own c ontroller that could acc omplish more sophistic ated instructions, like setting the sampling rate or resolution, which need to transfer two data bytes. for detailed information about the ps/2 protocol, please perform an appropriate search on various educational web sites. here we give a brief introduction: ? outline ps/2 protocol use two wires for bidirectional communication, one cl ock line and one data line. the ps/2 controller always ha s total control over the transmission line, but the ps/2 device generates clock signal during data transmission. 94 ? data transmit from the device to controller after sending an enabling instruction to the ps/2 mouse at stream mode, the device starts to send displacement data out, which consists of 33 bits. the frame data is cut into three similar slices, each of them containing a start bit (alw ays zero) and eight data bits (with lsb first), one parity check bit (odd check), and one stop bit (always one). ps/2 controller samples the data line at the fallin g edge of the ps/2 clock si gnal. this could easily be implemented using a shift register of 33 bits , but be cautious with the clock domain crossing problem. ? data transmit from the controller to device whenever the controller wants to transmit data to de vice, it first pulls the clock line low for more than one clock cycle to inhibit the current transmit process or to indicate the start of a new transmit process, which usually be called as inhibit state. after that, it pulls low the data line then release the clock line, and this is called th e request state. the rising edge on the clock line formed by the release action can also be used to indicate the samp le time point as for a 'start bit. the device will detect this succession and generates a clock seque nce in less than 10ms time. the transmit data consists of 12bits, one start bit (as explained before), eight data bits, one par ity check bit (odd check), one stop bit (alw ays one), and one acknowle dge bit (always zero). after sending out the parity check bit, the controller should release th e data line, and the device will detect any state change on the data line in the next clock cycle. if there?s no change on the data line for one clock cycle, the device will pull low the data line again as an acknowledgement which means that the data is correctly received. after the power on cycle of the ps/2 mouse, it ente rs into stream mode automatically and disable data transmit unless an enabling instruction is received. figure 6-16 shows the wa veform while communication happening on two lines. 95 figure 6-16 waveforms on two lines while communication taking place ? demonstration setup, file lo cations, and instructions ? project directory: de2_115_ps2_demo ? bit stream used : de2_115_ps2_demo.sof ? load the bit stream into fpga by executing de2_115_ps2_demo\demo_batch\de2_115_ps2_demo.bat ? plug in the ps/2 mouse ? press key[0] for enabling data transfer ? press key[1] to clear the display data cache you should see digital changes on 7-segment display when the ps/2 mouse moves, and the ledg[2:0] will blink respectively when the left-button, right-butt on or middle-button is pressed. table 6-2 gives the detailed inform ation. table 6-2 detailed information of the indicators indicator name description ledg[0] left button press indicator ledg[1] right button press indicator ledg[2] middle button press indicator 96 hex0 low byte of x displacement hex1 high byte of x displacement hex2 low byte of y displacement hex3 high byte of y displacement figure 6-17 illustrates the setup of this demonstration. figure 6-17 the setup of the ps/2 mouse demonstration 6 6 . . 9 9 i i r r r r e e c c e e i i v v e e r r d d e e m m o o n n s s t t r r a a t t i i o o n n in this demonstration, the key-related inform ation that the user has pressed on the remote controller( figure 6-18 table 6-3 ) will be dis played on the de2-115 board. users only need to point the remote controller to th e ir receiver on de2-115 board a nd press the key. after the signal being decoded and processed through fpga, the related information will be displayed on the 7-segment displays in hexadecimal format, which contains custom code, key code and inversed key code. the custom code and key code are used to identify a remote controller and key on the remote controller, respectively. next we will introduce how this information bei ng decoded and then displayed in this demo. when a key on the remote controller is pressed, the remote controller will emit a standard frame, shown in figure 6-19 . the beginning of the fram e is the lead c ode represents the start bit, and then is the key-related information, a nd the last 1 bit end code repr esents the end of the frame. 97 figure 6-18 remote controller table 6-3 key code information for each key on remote controller lead code 1bit custom code 16bits key code 8bits inv key code 8bits end code 1bit figure 6-19 the transmitting frame of the ir remote controller key key code key key code key key code key key code 0x0f 0x13 0x10 0x12 0x01 0x02 0x03 0x1a 0x04 0x05 0x06 0x1e 0x07 0x08 0x09 0x1b 0x11 0x00 0x17 0x1f 0x16 0x14 0x18 0x0c 98 after the ir receiver on de2-115 board receives this frame, it will directly transmit that to fpga. in this demo, the ip of ir receiver controller is implemented in the fpga. as figure 6-20 shows, it includes code detector , state machine, and shift re gister. first, the ir receiver demodulates the signal inputs to code detector block .the code detector block will check the lead code and feedback the examination result to state machine block. the state machine block will ch ange the state from idle to guidance once the lead code is detected. once the code detector has detected the custom code status, the current state will change from guidance to dataread state. at this state, the code detector will save the custom code and key/inv key code and output to shift regist er then displays it on 7-segment displays. figure 6-21 shows the state shift diagram of state machin e block. note that the input clock should be 50mhz. figure 6-20 the ir receiver controller figure 6-21 state shift diagram of state machine 99 we can apply the ir receiver to many applications , such as integrating to the sd card demo, and you can also develop other related in teresting applications with it. ? demonstration setup, file lo cations, and instructions ? project directory: de2_115_ir ? bit stream used: de2_115_ir.sof ? load the bit stream into the fpga by executing de2_115_ir\demo_batch\de2_115_ir.bat file ? point the ir receiver with the remo te-controller and press any button table 6-4 shows how the received code and key data display on eight 7-segm ent displays. table 6-4 detailed information of the indicators indicator name description hex0 inversed low byte of key code hex1 inversed high byte of key code hex2 low byte of key code hex3 high byte of key code hex4 low byte of custom code hex5 high byte of custom code hex6 repeated low byte of custom code hex7 repeated high byte of custom code figure 6-22 illustrates the setup for this demonstration. figure 6-22 the setup of the ir receiver demonstration 100 6 6 . . 1 1 0 0 m m u u s s i i c c s s y y n n t t h h e e s s i i z z e e r r d d e e m m o o n n s s t t r r a a t t i i o o n n this demonstration shows how to implement a multi-tone electronic keyboard using de2-115 board with a ps/2 keyboard and a speaker. ps/2 keyboard is used as the pi ano keyboard for input. the cyclone iv e fpga on the de2-115 board serves as the music synthe sizer soc to generate music and tones. the vga connected to the de2-115 board is used to show which key is pressed during the pl aying of the music. figure 6-23 shows the block diagram of the design of th e music synthes izer. there are four major blocks in the circuit: demo_sound, ps2_k eyboard, staff, and tone_generator. the demo_sound block stores a demo sound for user s to play; ps2_keyboard handles the users? input from ps/2 keyboard; the staff block dr aws the corresponding keyboard diagram on vga monitor when key(s) are pressed. the tone_gener ator is the core of music synthesizer soc. users can switch the music source either from ps2_keyboad or the demo_sound block using sw9. to repeat the demo sound, users can press key1. the tone_generator has two t ones: (1) string. (2) brass, wh ich is controlled by sw0. the audio codec used on the de2-115 board has two ch annels, which can be turned on/off using sw1 and sw2. figure 6-24 illus trates the setup for this demonstration. 101 figure 6-23 block diagram of the music synthesizer design ? demonstration setup, file lo cations, and instructions ? project directory: de2_115_synthesizer ? bit stream used: de2_115_synthesizer .sof or de2-115_synthesizer.pof ? connect a ps/2 keyboard to the de2-115 board. ? connect the vga output of the de2-115 board to a vga monitor (both lcd and crt type of monitors should work) ? connect the lineout of the de2-115 board to a speaker. ? load the bit stream into fpga by executing de2_115_synthesizer\demo_batch\de 2_115_synthesizer.bat file ? make sure all the switches (sw[9:0 ]) are set to 0 (down position) ? press key1 on the de2-115 board to start the music demo ? press key0 on the de2-115 board to reset the circuit note: if the hsmc loopback adapter is mounted, the i2c_scl will be directly routed back to i2c_sda. because audio chip, tv decoder chip and hsmc share one i2c bus, therefore audio and video chip won?t function correctly. 102 table 6-5 and table 6-6 illus trate the usage of the slide switches, push-button switches (keys), ps/2 keyboard. ? slide switches and push-buttons switches table 6-5 usage of the slide switches and push-buttons switches (keys) signal name description key[0] reset circuit key[1] repeat the demo music sw[0] off: brass, on: string sw[9] off: demo, on: ps/2 keyboard sw[1] channel-1 on / off sw[2] channel-2 on / off ? ps/2 keyboard table 6-6 usage of the ps/2 keyboard keys signal name description q -#4 a -5 w -#5 s -6 e -#6 d -7 f 1 t #1 g 2 y #2 h 3 j 4 i #4 k 5 o #5 l 6 p #6 : 7 ? +1 103 figure 6-24 the setup of the music synthesizer demonstration 6 6 . . 1 1 1 1 a a u u d d i i o o r r e e c c o o r r d d i i n n g g a a n n d d p p l l a a y y i i n n g g this demonstration shows how to implement an a udio recorder and player using the de2-115 board with the built-in audio codec chip. this demons tration is developed based on sopc builder and nios ii ide. figure 6-25 shows the m an-machine interf ace of this demonstration. two push-buttons and six slide switches are used for user s to configure this audi o system: sw0 is used to specify recording source to be line-in or mi c-in. sw1 is used to enable/disable mic boost when the recording source is mic-in. sw2 is used to enable/disable zero-cross detection for audio playing. sw3, sw4, and sw5 are used to specify recording sample rate as 96k, 48k, 44.1k, 32k, or 8k. the 16x2 lcd is used to indicate the r ecording/playing status. the 7-seg is used to display recording/playing duration with time unit in 1/100 second. the led is used to indicate the audio signal strength. table 6-7 and table 6-8 summarize the usa ge of slide switches for configuring the audio recorder and player. 104 figure 6-25 man-machine interface of audio recorder and player figure 6-26 shows the block diagram of the audio recorder and player design. there are hardware and software parts in the block di agram. the software part stores the nios ii program in sram. the software part is built by nios ii ide in c programming language. the hardware part is built by sopc builder under quartus ii. the hardware pa rt includes all the ot her blocks. the ?audio controller? is a user-defined sopc component. it is designed to se nd audio data to the audio chip or receive audio data from the audio chip. the audio chip is programmed through i2c protocol which is implemented in c code. the i2c pins from audio chip are connected to sopc system in terconnect fabric through pi o controllers. in this example, the audio chip is configured in master mode. the audio in terface is configured as i2s and 16-bit mode. 18.432mhz clock genera ted by the pll is connected to the xti/mclk pin of the audio chip through the audio controller. figure 6-26 block diagram of the audio recorder and player 105 ? demonstration setup, file lo cations, and instructions ? hardware project di rectory: de2_115_audio ? bit stream used: de2_115_audio.sof ? software project direct ory: de2_115_audio\software\ ? connect an audio source to the line-in port of the de2-115 board. ? connect a microphone to mic -in port on the de2-115 board. ? connect a speaker or headset to line-out port on the de2-115 board. ? load the bit stream into fpga. (note *1) ? load the software execution file into fpga. (note *1) ? configure audio with the slide switches. ? press key3 on the de2-115 board to st art/stop audio recoding (note *2) ? press key2 on the de2-115 board to start/stop audio playing (note *3) note: (1). execute de2_115_audio\demo_batch\audi o.bat will download .sof and .elf files. (2). recording process will stop if audio buffer is full. (3). playing process will stop if audio data is played completely. (4).if the hsmc loopback adapter is mounted, th e i2c_scl will be directly routed back to i2c_sda. because audio chip, tv decoder chip and hsmc share one i2c bus, therefore audio and video chip won?t function correctly. table 6-7 slide switches usage for audio source and signal processing setting slide switches 0 ? down position 1 ? up position sw0 audio is from mic audio is from line-in sw1 disable mic boost enable mic boost sw2 disable zero-cross detection enable zero-cross detection table 6-8 slide switch setting for sample rate switching for audio recorder and player sw5 (0 ? down; 1- up) sw4 (0 ? down; 1-up) sw3 (0 ? down; 1-up) sample rate 0 0 0 96k 0 0 1 48k 0 1 0 44.1k 0 1 1 32k 1 0 0 8k unlisted combination 96k 106 6 6 . . 1 1 2 2 w w e e b b s s e e r r v v e e r r d d e e m m o o n n s s t t r r a a t t i i o o n n this design example shows a http server using the sockets interface of the nichestack? tcp/ip stack nios ii edition on microc/os-ii to serve we b content from the de2-115 board. the server can process basic requests to serve html, jpeg, gif, png, js, css, swf, ico files from the altera read-only .zip file system . additionally, it allows users to control various board components from the web page. as part of the nios ii eds, nichestack? tcp/ip network st ack is a complete networking software suite designed to provide an optimal solution for network related applications accompany nios ii. using this demo, we assume that you already have a basic knowledge of tcp/ip protocols. the following describes the related sopc system. the sopc system used in this demo contains nios ii processor, on-chip memory, jtag uart, ti mer, triple-speed ethernet, scatter-gather dma controller and other peripherals etc. in the configuration page of the altera triple-speed ethernet controller, users can either set the mac interface as mii or rgmii as shown in figure 6-27 and figure 6-28 respectively . 107 figure 6-27 mii interface mac configuration 108 figure 6-28 rgmii interface mac configuration in the mac options tab (see figure 6-29 ), users should set up proper values for the phy chip 88e1111. the mdio module should be included, as it is used to generate a 2.5mhz mdc clock for the phy chip from the controller's source clock(he re a 100mhz clock source is expected) to divide the mac control register interface clock to pr oduce the mdc clock output on the mdio interface. the mac control register interface clock fre quency is 100mhz and the desired mdc clock frequency is 2.5mhz, so a host cloc k divisor of 40 should be used. 109 figure 6-29 mac options configuration once the triple-speed ethernet ip configuration ha s been set and necessary hardware connections have been made as shown in figure 6-30 , click on generate. 110 figure 6-30 sopc builder figure 6-31 shows the connections for programmable 10/100mbps ethernet operation via mii. figure 6-31 phy connected to the mac via mii figure 6-32 shows the connections for programma ble 10/100/1000mbps ethernet operation via rgmii. 111 figure 6-32 phy connected to the mac via rgmii after the sopc hardware project has been built, develop the sopc software project, whose basic architecture is shown in figure 6-33 . the top block contains the nios ii processor and the necessa ry hardware to be implemented into the de2-115 host board. the software device drivers contain the necessary device drivers needed for the ethernet and other hardware components to work. the hal api block provides the interface for the software device drivers, while the micro c/os-ii provides communication services to the nichestack? and web server. the nichestack? tcp/ip stack software block provides networking services to the application block where it contains the tasks for web server. 112 nios ii processor software device drivers hal api microc/os-ii nichestack tcp/ip software component application specific system initialization web server application figure 6-33 nios ii program software architecture finally, the detail descriptions fo r software flow chart of the we b server program are listed in below: firstly, the web server program initiates the mac and net device then calls the get_mac_addr() function to set the mac addresses for the phy. sec ondly, it initiates the au to-negotiation process to check the link between phy and ga teway device. if the link exists , the phy and gateway devices will broadcast their transmission parameters, sp eed, and duplex mode. after the auto-negotiation process has finished, it will establish the link. th irdly, the web server program will prepare the transmitting and receiving path for the link. if the path is created successfully, it will call the get_ip_addr() function to set up th e ip address for the network inte rface. after the ip address is successfully distributed, the niches tack? tcp/ip stack will start to run for web server application. figure 6-34 describes this dem o setup and connections on de2-115. the nios ii processor is running nichestack? on the microc/os-ii rtos. note: your gateway should support dhcp becaus e it uses dhcp protocol to request a valid ip from the gateway, or else you would need to reconfigure the system library to use static ip assignment. furthermore, the web server demo nstration uses the rgmii or mii interface to access the tcp/ip. you can switch the mac in terface via jp1 and jp2 for ethernet 0 and 113 ethernet 1 respectively. table 6-9 shows the project name of web server demonstration for each ethernet port and working mode. table 6-9 demo directory paths phy project directory interface enet0 enet1 rgmii interface de2_115_web_server\ de2_115_web_server_rgmii_enet0 de2_115_web_server\ de2_115_web_server_rgmii_enet1 mii interface de2_115_web_server\ de2_115_web_server_mii_enet0 de2_115_web_server\ de2_115_web_server_mii_enet1 ? demonstration setup, file lo cations, and instructions the following steps describe how to setup a web server demonstration on the enet0 in rgmii mode. ? project directory: de2_115_web_serve r\ de2_115_web_server_rgmii_enet0 ? nios ii project workspace: project directory\software ? bit stream used: de2_115_web_server.sof ? web site content zip file: ro_zipfs.zip ? make sure the phy device is working on rgm ii mode (short pin 1 and pin 2 of jp1) ? launch quartus ii and download the we b server demo bit stream into fpga ? launch nios ii ide and open the nios ii project workspace ? download the web site content zip file into flash memory using the flash programmer in nios ii ide ? plug a cat 5e cable into the ethern et port (j4) on the de2-115 board ? select ?run->run as nios ii hardware? in nios ii ide window to run th is project (note *) ? once the lcd on de2-115 board shows the valid ip address got from gateway, then launch your web browser ? input the ip into your browser. (ip is shown on the lcd display) ? you will see the brand new de2-115 webpage on your computer ? on the web page, you could access the de2-115 board?s peripherals from the left sidebar or link to external pages from the right sidebar. try ch eck some leds on the left sidebar and then press send will light up the specified leds on board. you also could send text to the lcd or set the value for 7-segment displays on de2-115 board. figure 6-35 gives a snapshot of the web server page 114 note: or execute de2_115_web_server\ 115 chapter 7 appendix 7 7 . . 1 1 r r e e v v i i s s i i o o n n h h i i s s t t o o r r y y version change log v1.0 initial version (preliminary) v1.01 vga vertical timing table correction sdram table reference modification v1.02 modify table4-15 header info. 7 7 . . 2 2 c c o o p p y y r r i i g g h h t t s s t t a a t t e e m m e e n n t t copyright ? 2010 terasic technologies. all rights reserved. |
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